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    Wall clock timer and system for generic modem
    1.
    发明授权
    Wall clock timer and system for generic modem 失效
    墙钟计时器和通用调制解调器系统

    公开(公告)号：US08787433B2

    公开(公告)日：2014-07-22

    申请号：US12261937

    申请日：2008-10-30

    申请人： Arunava Chaudhuri ,  Iwen Yao ,  Jeremy H. Lin ,  Remi Gurski

    发明人： Arunava Chaudhuri ,  Iwen Yao ,  Jeremy H. Lin ,  Remi Gurski

    IPC分类号： H04B1/38 ,  H04L12/28

    CPC分类号： H04B1/406

    摘要： A modem (for example, a modem within a cellular telephone) includes a plurality of Wireless Communication System Modem Sub-Circuits (WCSMSCs). Each WCSMSC receives a control signal generated by a corresponding one of a plurality of programmable timers. Each timer receives the same sequence of count values from a wall clock counter. A processor that controls overall modem operation can program a timer to generate a control pulse at a particular count time of the wall clock counter. The processor can also program a timer to generate a periodic control signal. The control signals output from the timers orchestrate when the various WCSMSCs start operating in the processing of a frame. By virtue of the programmability of the timers, the wall clock timer system is programmable to generate customized control signals such that frames of new and different protocols having arbitrary frame structures can be processed by the same modem/timer system.

    摘要翻译： 调制解调器（例如，蜂窝电话中的调制解调器）包括多个无线通信系统调制解调器子电路（WCSMSC）。 每个WCSMSC接收由多个可编程定时器中相应的一个产生的控制信号。 每个定时器从挂钟计数器接收相同的计数值序列。 控制整个调制解调器操作的处理器可以编程定时器以在挂钟计数器的特定计数时间产生控制脉冲。 处理器还可以编程定时器以产生周期性控制信号。 当各种WCSMSC在帧的处理中开始运行时，从定时器输出的控制信号协调编排。 通过定时器的可编程性，挂钟计时器系统可编程以产生定制的控制信号，使得具有任意帧结构的新协议和不同协议的帧可以由相同的调制解调器/定时器系统来处理。

    Reconfigurable wireless modem sub-circuits to implement multiple air interface standards
    2.
    发明授权
    Reconfigurable wireless modem sub-circuits to implement multiple air interface standards 有权
    可重配置的无线调制解调器子电路实现多个空中接口标准

    公开(公告)号：US08520571B2

    公开(公告)日：2013-08-27

    申请号：US12396270

    申请日：2009-03-02

    申请人： Arunava Chaudhuri ,  Iwen Yao ,  Jeremy H. Lin ,  Ali RostamPisheh ,  Raghu Challa ,  Hemanth Sampath ,  Megan Wu ,  Joseph Zanotelli ,  Mrinal Nath

    发明人： Arunava Chaudhuri ,  Iwen Yao ,  Jeremy H. Lin ,  Ali RostamPisheh ,  Raghu Challa ,  Hemanth Sampath ,  Megan Wu ,  Joseph Zanotelli ,  Mrinal Nath

    IPC分类号： H04B7/00

    CPC分类号： G06F15/7842

    摘要： A flexible and reconfigurable digital system (for example, a wireless modem) includes a set of sub-circuits. Each sub-circuit includes a task manager and an amount of configurable hardware circuitry for performing a type of operation on a data stream. The task manager of a sub-circuit can configure and control the configurable hardware of the sub-circuit. A central processor configures and orchestrates operation of the sub-circuits by maintaining a set of task lists in a tightly coupled memory. Each task list includes task instructions for a corresponding sub-circuit. The task manager of a sub-circuit reads task instructions from its task list and controls its associated hardware circuitry as directed by the instructions. A timestamp task instruction and a push task instruction and the task list architecture allow modem sub-circuits to be easily reconfigured to operate in accordance with either a first air interface standard or a second air interface standard.

    摘要翻译： 灵活和可重新配置的数字系统（例如，无线调制解调器）包括一组子电路。 每个子电路包括任务管理器和用于对数据流执行一种操作的可配置硬件电路的量。 子电路的任务管理器可以配置和控制子电路的可配置硬件。 中央处理器通过在紧耦合存储器中维护一组任务列表来配置和协调子电路的操作。 每个任务列表包括相应子电路的任务指令。 子电路的任务管理器从其任务列表读取任务指令，并根据指令控制其相关联的硬件电路。 时间戳任务指令和推送任务指令以及任务列表架构允许将调制解调器子电路轻松地重新配置为根据第一空中接口标准或第二空中接口标准进行操作。

    ACCESSING MEMORY DURING PARALLEL TURBO DECODING
    3.
    发明申请
    ACCESSING MEMORY DURING PARALLEL TURBO DECODING 失效
    并行涡轮解码期间的访问记忆

    公开(公告)号：US20120066566A1

    公开(公告)日：2012-03-15

    申请号：US12878934

    申请日：2010-09-09

    申请人： Zhiqiang Cui ,  Iwen Yao ,  Qiang Huang

    发明人： Zhiqiang Cui ,  Iwen Yao ,  Qiang Huang

    IPC分类号： H03M13/05 ,  G06F11/10

    CPC分类号： H03M13/2984 ,  H03M13/2707 ,  H03M13/2775 ,  H03M13/3905 ,  H03M13/3972 ,  H03M13/6566

    摘要： A method for accessing extrinsic information in a turbo decoder is disclosed. Operation phases for Forward State Metric Calculators (FSMCs) and Reverse State Metric Calculators (RSMCs) in multiple maximum a posteriori probability (MAP) decoders are misaligned differently based on whether a current half iteration is even or odd. First extrinsic information is read from a memory into the FSMCs and RSMCs using the misaligned operation phases. Second extrinsic information is determined using the MAP decoders. Each row of the second extrinsic information is stored to a different bank in the memory using the misaligned operation phases.

    摘要翻译： 公开了一种在turbo解码器中访问外部信息的方法。 基于当前半迭代是偶数还是奇数，多个最大后验概率（MAP）解码器中的前向状态度量计算器（FSMC）和反向状态度量计算器（RSMC）的操作阶段不对齐。 使用不对齐的操作阶段，将第一外部信息从存储器读入FSMC和RSMC。 使用MAP解码器确定第二外在信息。 使用未对准的操作阶段将第二外在信息的每一行存储在存储器中的不同存储体中。

    METHOD AND SYSTEM FOR DC COMPENSTATION
    4.
    发明申请
    METHOD AND SYSTEM FOR DC COMPENSTATION 有权
    直流电压的方法和系统

    公开(公告)号：US20100184397A1

    公开(公告)日：2010-07-22

    申请号：US12398285

    申请日：2009-03-05

    申请人： Tamer A. Kadous ,  Iwen Yao ,  Jibing Wang ,  Weihong Jing ,  Yong Li

    发明人： Tamer A. Kadous ,  Iwen Yao ,  Jibing Wang ,  Weihong Jing ,  Yong Li

    IPC分类号： H04B7/00

    CPC分类号： H04L25/061 ,  H03G3/3068 ,  H03G3/3078

    摘要： A technique for performing AGC and DC compensation in a receiver. The receiver comprises an energy estimator for generating an estimate of the level of a received signal; an RF device to apply gain to the received signal; an AGC for controlling the RF device gain based on the energy estimation; a first DC compensation loop for finely adjusting the DC component of the received signal in fast or slow tracking mode (FTM or STM); and a second DC compensation loop for coarsely adjusting the DC component of the received signal. Three modes of AGC operations: In Acquisition, iterations of FTM fine DC adjustment, short energy estimation, and RF device gain adjustment are performed during signal timing detection. In Connected, long energy estimation, RF device gain adjustment, and STM fine and coarse DC adjustments are performed during superframe preamble. In Sleep, FTM fine DC adjustment, short energy estimation, and RF device gain adjustment are performed during superframe preamble.

    摘要翻译： 一种用于在接收机中执行AGC和DC补偿的技术。 接收机包括用于产生接收信号电平的估计的能量估计器; 用于向接收到的信号施加增益的RF设备; 用于基于能量估计来控制RF设备增益的AGC; 用于以快速或慢速跟踪模式（FTM或STM）精细调整接收信号的DC分量的第一DC补偿环路; 以及用于粗调整接收信号的DC分量的第二DC补偿环路。 AGC操作的三种模式：在采集中，在信号定时检测期间执行FTM精细直流调节的迭代，短能量估计和RF器件增益调整。 在连接中，在超帧前导码期间执行长能量估计，RF设备增益调整和STM精细和粗略的DC调整。 在睡眠状态下，在超帧前缀中执行FTM精细直流调整，短能量估计和RF器件增益调整。

    Method and system for DC compensation and AGC
    5.
    发明授权
    Method and system for DC compensation and AGC 有权
    直流补偿和AGC的方法和系统

    公开(公告)号：US08331892B2

    公开(公告)日：2012-12-11

    申请号：US12398285

    申请日：2009-03-05

    申请人： Tamer A. Kadous ,  Iwen Yao ,  Jibing Wang ,  Weihong Jing ,  Yong Li

    发明人： Tamer A. Kadous ,  Iwen Yao ,  Jibing Wang ,  Weihong Jing ,  Yong Li

    IPC分类号： H04B1/10

    CPC分类号： H04L25/061 ,  H03G3/3068 ,  H03G3/3078

    摘要： A technique for performing AGC and DC compensation in a receiver. The receiver comprises an energy estimator for generating an estimate of the level of a received signal; an RF device to apply gain to the received signal; an AGC for controlling the RF device gain based on the energy estimation; a first DC compensation loop for finely adjusting the DC component of the received signal in fast or slow tracking mode (FTM or STM); and a second DC compensation loop for coarsely adjusting the DC component of the received signal. Three modes of AGC operations: In Acquisition, iterations of FTM fine DC adjustment, short energy estimation, and RF device gain adjustment are performed during signal timing detection. In Connected, long energy estimation, RF device gain adjustment, and STM fine and coarse DC adjustments are performed during superframe preamble. In Sleep, FTM fine DC adjustment, short energy estimation, and RF device gain adjustment are performed during superframe preamble.

    摘要翻译： 一种用于在接收机中执行AGC和DC补偿的技术。 接收机包括用于产生接收信号电平的估计的能量估计器; 用于向接收到的信号施加增益的RF设备; 用于基于能量估计来控制RF设备增益的AGC; 用于以快速或慢速跟踪模式（FTM或STM）精细调整接收信号的DC分量的第一DC补偿环路; 以及用于粗调整接收信号的DC分量的第二DC补偿环路。 AGC操作的三种模式：在采集中，在信号定时检测期间执行FTM精细直流调节的迭代，短能量估计和RF器件增益调整。 在连接中，在超帧前导码期间执行长能量估计，RF设备增益调整和STM精细和粗略的DC调整。 在睡眠状态下，在超帧前缀中执行FTM精细直流调整，短能量估计和RF器件增益调整。

    Interleaver for turbo decoder
    8.
    发明授权
    Interleaver for turbo decoder 有权
    turbo解码器的交织器

    公开(公告)号：US06845482B2

    公开(公告)日：2005-01-18

    申请号：US09853332

    申请日：2001-05-10

    申请人： Iwen Yao ,  Da-Shan Shiu

    发明人： Iwen Yao ,  Da-Shan Shiu

    IPC分类号： H03M13/27 ,  H03M13/29 ,  H04L1/00 ,  H04L5/02 ,  H03M13/00

    CPC分类号： H04L5/023 ,  H03M13/2714 ,  H03M13/2764 ,  H03M13/2789 ,  H03M13/2957 ,  H04L1/005 ,  H04L1/0066

    摘要： Techniques to efficiently generate memory addresses for a Turbo code interleaver using a number of look-up tables. An interleaver includes a storage unit, sets of tables, and an address generator. The storage unit stores K elements for a data packet at locations representative of an R×C array, with the elements being stored in a first (e.g., linear) order and provided in a second (e.g., interleaved) order. A first set of table(s) stores sequences (e.g., inter-row permutation sequences PA, PB, PC, and PD) used to perform row permutation of the array to map from the first order to the second order. A second set of table(s) stores sequences (e.g., intra-row base sequences and prime number sequences) used to perform column permutation. The address generator receives a first address for the first order and generates a corresponding second address for the second order based on sequences stored in the tables.

    摘要翻译： 使用多个查找表有效地生成Turbo码交织器的存储器地址的技术。 交织器包括存储单元，表格集和地址生成器。 存储单元在表示RxC阵列的位置处存储用于数据分组的K个元素，其中元素以第一（例如，线性）顺序存储，并以第二（例如交错）顺序提供。 第一组表存储用于执行阵列的行排列以从第一次到第二次映射的序列（例如，行间置换序列PA，PB，PC和PD）。 第二组表存储用于执行列排列的序列（例如，行内碱基序列和素数序列）。 地址生成器接收第一顺序的第一地址，并且基于存储在表中的序列来生成二阶对应的第二地址。

    Off-line task list architecture utilizing tightly coupled memory system
    10.
    发明授权
    Off-line task list architecture utilizing tightly coupled memory system 有权
    使用紧密耦合的存储器系统的离线任务列表架构

    公开(公告)号：US08458380B2

    公开(公告)日：2013-06-04

    申请号：US12396217

    申请日：2009-03-02

    申请人： Arunava Chaudhuri ,  Iwen Yao ,  Jeremy H. Lin ,  Remi Gurski ,  Kevin W. Yen

    发明人： Arunava Chaudhuri ,  Iwen Yao ,  Jeremy H. Lin ,  Remi Gurski ,  Kevin W. Yen

    IPC分类号： G06F3/00 ,  G06F9/46

    CPC分类号： G06F9/3879 ,  G06F15/7814

    摘要： A flexible and reconfigurable digital system (for example, a wireless modem) includes a set of sub-circuits. Each sub-circuit includes a task manager and an amount of configurable hardware circuitry for performing a type of operation on a data stream. The task manager of a sub-circuit can configure and control the configurable hardware of the sub-circuit. A central processor configures and orchestrates operation of the sub-circuits by maintaining a set of task lists in a tightly coupled memory. Each task list includes task instructions for a corresponding sub-circuit. The task manager of a sub-circuit reads task instructions from its task list and controls its associated hardware circuitry as directed by the instructions. A timestamp task instruction and a push task instruction and the task list architecture allow modem sub-circuits to be easily reconfigured to operate in accordance with either a first air interface standard or a second air interface standard.

    摘要翻译： 灵活和可重新配置的数字系统（例如，无线调制解调器）包括一组子电路。 每个子电路包括任务管理器和用于对数据流执行一种操作的可配置硬件电路的量。 子电路的任务管理器可以配置和控制子电路的可配置硬件。 中央处理器通过在紧耦合存储器中维护一组任务列表来配置和协调子电路的操作。 每个任务列表包括相应子电路的任务指令。 子电路的任务管理器从其任务列表读取任务指令，并根据指令控制其相关联的硬件电路。 时间戳任务指令和推送任务指令以及任务列表架构允许将调制解调器子电路轻松地重新配置为根据第一空中接口标准或第二空中接口标准进行操作。