公开(公告)号：US20240006487A1

公开(公告)日：2024-01-04

申请号：US18469799

申请日：2023-09-19

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kodai OZAWA ,  Sho NAKANISHI

IPC: H01L29/08 ,  H01L29/739 ,  H01L29/861

CPC classification number: H01L29/0808 ,  H01L29/8611 ,  H01L29/7393

Abstract: The semiconductor device has the main surface, the semiconductor substrate having the first impurity region formed on the main surface, the first electrode formed on the main surface having the first impurity region, the insulating film formed on the main surface such that surround the first electrode, the second electrode formed on the insulating film such that spaced apart from the first electrode and annularly surround the first electrode, and the semi-insulating film. The first electrode has the outer peripheral edge portion. The semi-insulating film is continuously formed from on the outer peripheral edge portion to on the second electrode. The outer peripheral edge portion includes the first corner portion. The second electrode has the second corner portion facing the first corner portion. The semi-insulating film on the insulating film is removed between the first corner and the second corner portion.

公开(公告)号：US20230387064A1

公开(公告)日：2023-11-30

申请号：US18188084

申请日：2023-03-22

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kodai OZAWA ,  Sho NAKANISHI

IPC: H01L23/00 ,  H01L23/495 ,  H01L23/485

CPC classification number: H01L24/32 ,  H01L23/49513 ,  H01L23/485 ,  H01L2224/32245 ,  H01L2924/1815 ,  H01L2924/13055 ,  H01L2924/1203 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L29/0607

Abstract: A semiconductor device includes a lead, a semiconductor substrate, a back-surface electrode provided between the semiconductor substrate and the lead, and a solder layer configured to connect the back-surface electrode and the lead. The back-surface electrode includes a silicide layer formed on a back surface of the semiconductor substrate, a bonding layer formed on the lead, a barrier layer formed on the bonding layer, and a stress relaxation layer formed between the silicide layer and the barrier layer. The stress relaxation layer is made of a first metal film containing aluminum as a main component or a second metal film containing gold, silver, or copper as a main component.

公开(公告)号：US20230268182A1

公开(公告)日：2023-08-24

申请号：US17993313

申请日：2022-11-23

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Sho NAKANISHI ,  Kodai OZAWA

IPC: H01L21/285 ,  H01L29/45 ,  H01L29/78

CPC classification number: H01L21/28518 ,  H01L29/45 ,  H01L29/7813

Abstract: Disclosed is a technique for enhancing adhesion between a semiconductor substrate and a back surface electrode covering the back surface thereof. In particular, the enhancing adhesion technique includes: providing a semiconductor substrate SB having a main surface and a back surface opposite to the main surface, the back surface including n-type silicon; forming a first metal layer on the back surface of the semiconductor substrate SB, the first metal layer including nickel and vanadium which has a thermal diffusion coefficient smaller than that of nickel; performing a heat treatment to the semiconductor substrate to react silicon contained in the semiconductor substrate with nickel contained in the first metal layer to form a NiSiV layer in contact with the back surface of the semiconductor substrate; and forming a second metal including titanium on the NiSiV layer.

公开(公告)号：US20220140077A1

公开(公告)日：2022-05-05

申请号：US17516104

申请日：2021-11-01

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kodai OZAWA ,  Sho NAKANISHI

IPC: H01L29/08 ,  H01L29/861 ,  H01L29/739

Abstract: The semiconductor device has the main surface, the semiconductor substrate having the first impurity region formed on the main surface, the first electrode formed on the main surface having the first impurity region, the insulating film formed on the main surface such that surround the first electrode, the second electrode formed on the insulating film such that spaced apart from the first electrode and annularly surround the first electrode, and the semi-insulating film. The first electrode has the outer peripheral edge portion. The semi-insulating film is continuously formed from on the outer peripheral edge portion to on the second electrode. The outer peripheral edge portion includes the first corner portion. The second electrode has the second corner portion facing the first corner portion. The semi-insulating film on the insulating film is removed between the first corner and the second corner portion.

公开(公告)号：US20240387649A1

公开(公告)日：2024-11-21

申请号：US18613754

申请日：2024-03-22

Applicant: Renesas Electronics Corporation

Inventor： Kodai OZAWA

IPC: H01L29/40 ,  H01L29/739 ,  H01L29/861

Abstract: A semiconductor device capable of suppressing variation in breakdown voltage is provided. The semiconductor device includes a semiconductor substrate, an insulating film, a first electrode and a second electrode, and a semi-insulating film. The semiconductor substrate has a first surface. The semiconductor substrate has, in plan view, an element region and a termination region surrounding the element region. The semiconductor substrate has a first impurity region formed on a first surface in the termination region. The semi-insulating film is disposed so as to extend over the insulating film between the first electrode and the second electrode in plan view. The semi-insulating film includes silicon and nitrogen.

公开(公告)号：US20240162305A1

公开(公告)日：2024-05-16

申请号：US18054996

申请日：2022-11-14

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kodai OZAWA ,  Sho NAKANISHI

IPC: H01L29/40 ,  H01L29/06

CPC classification number: H01L29/404 ,  H01L29/0623 ,  H01L29/401

Abstract: A manufacturing method of a semiconductor device includes: (a) preparing a semiconductor substrate of a first conductivity type having an upper surface and a lower surface; (b) after the (a), forming an interlayer dielectric film on the upper surface of the semiconductor substrate; (c) after the (b), forming a base film on the interlayer dielectric film; (d) after the (c), forming a first conductive film on the base film; (e) after the (d), patterning the first conductive film to form a first wiring and a second wiring next to the first wiring; and (f) after the (e), removing the base film located between the first wiring and the second wiring. A material constituting the base film is different from a material constituting the first conductive film.