知搜-全球专利检索

  1. 登录
  2. 注册

搜索结果

14 条记录 (耗时 0.024 秒)

    Semiconductor integrated circuit device
    7.
    发明授权
    Semiconductor integrated circuit device 有权
    半导体集成电路器件

    公开(公告)号：US09214217B2

    公开(公告)日：2015-12-15

    申请号：US14450247

    申请日：2014-08-03

    申请人： Renesas Electronics Corporation

    发明人： Natsuki Ikehata ,  Kazuo Tanaka ,  Takeo Toba ,  Masashi Arakawa

    IPC分类号： H03F3/45 ,  G11C11/4076 ,  G11C7/10 ,  G11C11/4093 ,  G11C11/4096 ,  G11C11/4091

    CPC分类号： G11C11/4091 ,  G11C7/10 ,  G11C7/1057 ,  G11C7/1072 ,  G11C7/1084 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096

    摘要： An output signal characteristic of a differential amplifier circuit is improved. When an input data signal becomes ‘Low’, current flowing through a first transistor will decrease and potential at a connection (a node) between a first resistor and a second resistor will increase. This potential is input (negatively fed back) to the gate of a second transistor, and because this gate potential increases, a tail current amount is adjusted in an increasing direction. When the input data signal becomes ‘High’, the current of the first transistor increases and thus the potential at the node decreases. Thus, the gate potential (negative feedback) of the second transistor decreases, and the tail current amount is adjusted in a decreasing direction. Thus, in the rising and falling of an input waveform, the difference in a delay time with respect to the output waveform decreases, respectively.

    摘要翻译： 差分放大电路的输出信号特性得到改善。 当输入数据信号为“低”时，流过第一晶体管的电流将减小，并且第一电阻和第二电阻之间的连接（节点）的电位将增加。 该电位被输入（负反馈）到第二晶体管的栅极，并且由于该栅极电位增加，所以在增加的方向上调节尾部电流量。 当输入数据信号为“高”时，第一晶体管的电流增加，因此节点处的电位减小。 因此，第二晶体管的栅极电位（负反馈）减小，并且沿着减小的方向调整尾电流量。 因此，在输入波形的上升和下降中，延迟时间相对于输出波形的差别分别减小。

    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
    10.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权
    半导体集成电路设备

    公开(公告)号：US20140334240A1

    公开(公告)日：2014-11-13

    申请号：US14450247

    申请日：2014-08-03

    申请人： Renesas Electronics Corporation

    发明人： Natsuki Ikehata ,  Kazuo Tanaka ,  Takeo Toba ,  Masashi Arakawa

    IPC分类号： G11C11/4076 ,  G11C11/4091

    CPC分类号： G11C11/4091 ,  G11C7/10 ,  G11C7/1057 ,  G11C7/1072 ,  G11C7/1084 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096

    摘要： An output signal characteristic of a differential amplifier circuit is improved. When an input data signal becomes ‘Low’, current flowing through a first transistor will decrease and potential at a connection (a node) between a first resistor and a second resistor will increase. This potential is input (negatively fed back) to the gate of a second transistor, and because this gate potential increases, a tail current amount is adjusted in an increasing direction. When the input data signal becomes ‘High’, the current of the first transistor increases and thus the potential at the node decreases. Thus, the gate potential (negative feedback) of the second transistor decreases, and the tail current amount is adjusted in a decreasing direction. Thus, in the rising and falling of an input waveform, the difference in a delay time with respect to the output waveform decreases, respectively.

    摘要翻译： 差分放大电路的输出信号特性得到改善。 当输入数据信号为“低”时，流过第一晶体管的电流将减小，并且第一电阻和第二电阻之间的连接（节点）的电位将增加。 该电位被输入（负反馈）到第二晶体管的栅极，并且由于该栅极电位增加，所以在增加的方向上调节尾部电流量。 当输入数据信号为“高”时，第一晶体管的电流增加，因此节点处的电位减小。 因此，第二晶体管的栅极电位（负反馈）减小，并且沿着减小的方向调整尾电流量。 因此，在输入波形的上升和下降中，延迟时间相对于输出波形的差别分别减小。