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    Semiconductor device with high K dielectric control terminal spacer structure
    1.
    发明授权
    Semiconductor device with high K dielectric control terminal spacer structure 有权
    具有高K介质控制端子间隔结构的半导体器件

    公开(公告)号：US08349684B2

    公开(公告)日：2013-01-08

    申请号：US12622115

    申请日：2009-11-19

    申请人： Jin Cai ,  Amlan Majumdar ,  Ramachandran Muralidhar ,  Ghavam G. Shahidi

    发明人： Jin Cai ,  Amlan Majumdar ,  Ramachandran Muralidhar ,  Ghavam G. Shahidi

    IPC分类号： H01L21/336

    CPC分类号： H01L29/4983 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/7833

    摘要： A semiconductor device including a control terminal sidewall spacer structure made of a high-K dielectric material. The semiconductor device includes a control terminal where the spacer structure is a sidewall spacer structure for the control terminal. The semiconductor device includes current terminal regions located in a substrate. In some examples, the spacer structure has a height that is less than the height of the control terminal. In some examples, the spacer structure includes portions located over the regions of the substrate between the first current terminal region and the second current terminal region.

    摘要翻译： 一种半导体器件，包括由高K电介质材料制成的控制端子侧壁间隔结构。 半导体器件包括控制端子，其中间隔结构是用于控制端子的侧壁间隔结构。 半导体器件包括位于衬底中的电流端子区域。 在一些示例中，间隔结构的高度小于控制端的高度。 在一些示例中，间隔结构包括位于第一电流端子区域和第二电流端子区域之间的衬底的区域上方的部分。

    SEMICONDUCTOR DEVICE WITH HIGH K DIELECTRIC CONTROL TERMINAL SPACER STRUCTURE
    2.
    发明申请
    SEMICONDUCTOR DEVICE WITH HIGH K DIELECTRIC CONTROL TERMINAL SPACER STRUCTURE 有权
    具有高K介电控制终端间隔结构的半导体器件

    公开(公告)号：US20110117712A1

    公开(公告)日：2011-05-19

    申请号：US12622115

    申请日：2009-11-19

    申请人： RAMACHANDRAN MURALIDHAR ,  Jin Cai ,  Amlan Majumdar ,  Ghavam G. Shahidi

    发明人： RAMACHANDRAN MURALIDHAR ,  Jin Cai ,  Amlan Majumdar ,  Ghavam G. Shahidi

    IPC分类号： H01L21/336 ,  H01L21/28

    CPC分类号： H01L29/4983 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/7833

    摘要： A semiconductor device including a control terminal sidewall spacer structure made of a high-K dielectric material. The semiconductor device includes a control terminal where the spacer structure is a sidewall spacer structure for the control terminal. The semiconductor device includes current terminal regions located in a substrate. In some examples, the spacer structure has a height that is less than the height of the control terminal. In some examples, the spacer structure includes portions located over the regions of the substrate between the first current terminal region and the second current terminal region.

    摘要翻译： 一种半导体器件，包括由高K电介质材料制成的控制端子侧壁间隔结构。 半导体器件包括控制端子，其中间隔结构是用于控制端子的侧壁间隔结构。 半导体器件包括位于衬底中的电流端子区域。 在一些示例中，间隔结构的高度小于控制端的高度。 在一些示例中，间隔结构包括位于第一电流端子区域和第二电流端子区域之间的衬底的区域上方的部分。

    HARDENED TRANSISTORS IN SOI DEVICES
    3.
    发明申请
    HARDENED TRANSISTORS IN SOI DEVICES 审中-公开
    SOI器件中的硬化晶体管

    公开(公告)号：US20090072313A1

    公开(公告)日：2009-03-19

    申请号：US11857569

    申请日：2007-09-19

    申请人： Jin Cai ,  Wilfried E. Haensch ,  Tak H. Ning ,  Philip J. Oldiges ,  Ghavam G. Shahidi

    发明人： Jin Cai ,  Wilfried E. Haensch ,  Tak H. Ning ,  Philip J. Oldiges ,  Ghavam G. Shahidi

    IPC分类号： H01L27/12

    CPC分类号： H01L27/1203 ,  H01L21/823425 ,  H01L21/84 ,  H01L27/07 ,  H01L29/785 ,  H01L29/78612

    摘要： A series transistor device includes a series source, a series drain, a first constituent transistor, and a second constituent transistor. The first constituent transistor has a first source and a first drain, and the second constituent transistor has a second source and a second drain. All of the constituent transistors have a same conductivity type. The series source is the first source, and the series drain is the second drain. A drain of one of the constituent transistors is merged with a source of another of the constituent transistors.

    摘要翻译： 串联晶体管器件包括串联源极，串联漏极，第一构成晶体管和第二构成晶体管。 第一构成晶体管具有第一源极和第一漏极，并且第二构成晶体管具有第二源极和第二漏极。 所有构成晶体管都具有相同的导电类型。 串联源是第一个源，串联漏极是第二个漏极。 一个构成晶体管的漏极与另一个构成晶体管的源极合并。

    Semiconductor-on-insulator (SOI) substrates with ultra-thin SOI layers and buried oxides
    5.
    发明授权
    Semiconductor-on-insulator (SOI) substrates with ultra-thin SOI layers and buried oxides 有权
    具有超薄SOI层和掩埋氧化物的绝缘体上半导体（SOI）衬底

    公开(公告)号：US09059245B2

    公开(公告)日：2015-06-16

    申请号：US13483781

    申请日：2012-05-30

    申请人： Tze-Chiang Chen ,  Joel P. de Souza ,  Devendra K. Sadana ,  Ghavam G. Shahidi

    发明人： Tze-Chiang Chen ,  Joel P. de Souza ,  Devendra K. Sadana ,  Ghavam G. Shahidi

    IPC分类号： H01L21/76 ,  H01L21/762

    CPC分类号： H01L21/76243

    摘要： Semiconductor-on-insulator (SOI) substrates including a buried oxide (BOX) layer having a thickness of less than 300 Å are provided. The (SOI) substrates having the thin BOX layer are provided using a method including a step in which oxygen ions are implanted at high substrate temperatures (greater than 600° C.), and at a low implant energy (less than 40 keV). An anneal step in an oxidizing atmosphere follows the implant step and is performed at a temperature less than 1250° C. The anneal step in oxygen containing atmosphere converts the region containing implanted oxygen atoms formed by the implant step into a BOX having a thickness of less than 300 Å. In some instances, the top semiconductor layer of the SOI substrate has a thickness of less than 300 Å.

    摘要翻译： 提供了包括厚度小于300埃的掩埋氧化物（BOX）层的绝缘体上半导体（SOI）衬底。 使用包括以高衬底温度（大于600℃）和低注入能量（小于40keV）注入氧离子的步骤的方法提供具有薄BOX层的（SOI）衬底。 氧化气氛中的退火步骤遵循注入步骤，并且在低于1250℃的温度下进行。含氧气氛中的退火步骤将包含由注入步骤形成的注入的氧原子的区域转换成厚度较小的BOX 比300Å。 在一些情况下，SOI衬底的顶部半导体层具有小于300埃的厚度。

    Integrated circuit with a thin body field effect transistor and capacitor
    8.
    发明授权
    Integrated circuit with a thin body field effect transistor and capacitor 有权
    具有薄体场效应晶体管和电容器的集成电路

    公开(公告)号：US08659066B2

    公开(公告)日：2014-02-25

    申请号：US13345266

    申请日：2012-01-06

    申请人： Kangguo Cheng ,  Bruce Doris ,  Ali Khakifirooz ,  Ghavam G. Shahidi

    发明人： Kangguo Cheng ,  Bruce Doris ,  Ali Khakifirooz ,  Ghavam G. Shahidi

    IPC分类号： H01L27/06

    CPC分类号： H01L21/84 ,  H01L21/32053 ,  H01L21/823814 ,  H01L27/0629 ,  H01L27/1203 ,  H01L29/41783

    摘要： An integrated circuit includes a transistor and a capacitor. The transistor includes a first semiconductor layer and a gate stack located on the first semiconductor layer. The gate stack includes a metal layer and a first high-k dielectric layer. A gate spacer is located on sidewalls of the gate stack. The first high-k dielectric layer is located between the first semiconductor layer and the metal layer and between the gate spacer and sidewalls of the metal layer. A first silicide region is located on a first source/drain region. A second silicide region is located on a second source/drain region. The capacitor includes a first terminal that comprises a third silicide region located on a portion of the second semiconductor. A second high-k dielectric layer is located on the silicide region. A second terminal comprises a metal layer that is located on the second high-k dielectric layer.

    摘要翻译： 集成电路包括晶体管和电容器。 晶体管包括位于第一半导体层上的第一半导体层和栅极堆叠。 栅堆叠包括金属层和第一高k电介质层。 栅极间隔物位于栅极叠层的侧壁上。 第一高k电介质层位于第一半导体层和金属层之间以及栅间隔物和金属层的侧壁之间。 第一硅化物区域位于第一源极/漏极区域上。 第二硅化物区域位于第二源极/漏极区域上。 电容器包括第一端子，其包括位于第二半导体的一部分上的第三硅化物区域。 第二高k电介质层位于硅化物区域上。 第二端子包括位于第二高k电介质层上的金属层。

    Method to reduce ground-plane poisoning of extremely-thin SOI (ETSOI) layer with thin buried oxide
    10.
    发明授权
    Method to reduce ground-plane poisoning of extremely-thin SOI (ETSOI) layer with thin buried oxide 有权
    减少具有薄埋层氧化物的极薄SOI（ETSOI）层的接地面中毒的方法

    公开(公告)号：US08618554B2

    公开(公告)日：2013-12-31

    申请号：US12941771

    申请日：2010-11-08

    申请人： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam G. Shahidi

    发明人： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam G. Shahidi

    IPC分类号： H01L29/15

    CPC分类号： H01L29/78603 ,  H01L21/76254

    摘要： The present disclosure, which is directed to ultra-thin-body-and-BOX and Double BOX fully depleted SOI devices having an epitaxial diffusion-retarding semiconductor layer that slows dopant diffusion into the SOI channel, and a method of making these devices. Dopant concentrations in the SOI channels of the devices of the present disclosure having an epitaxial diffusion-retarding semiconductor layer between the substrate and SOI channel are approximately 50 times less than the dopant concentrations measured in SOI channels of devices without the epitaxial diffusion-retarding semiconductor layer.

    摘要翻译： 涉及超薄体BOX和双BOX完全耗尽的SOI器件的本公开内容，以及制造这些器件的方法，其具有外延扩散延迟半导体层，其减缓掺杂剂扩散到SOI沟道中。 具有在衬底和SOI沟道之间的外延扩散延迟半导体层的本公开的器件的SOI沟道中的掺杂剂浓度比在没有外延扩散延迟半导体层的器件的SOI沟道中测量的掺杂剂浓度大约小50倍 。