公开(公告)号：US20130271566A1

公开(公告)日：2013-10-17

申请号：US13839447

申请日：2013-03-15

Applicant: QUALCOMM INCORPORATED

Inventor： Ying CHEN ,  Li ZHANG ,  Yang YU ,  Geert VAN DER AUWERA ,  Xiang LI ,  Marta KARCZEWICZ

IPC: H04N13/00

CPC classification number: H04N13/161 ,  H04N19/109 ,  H04N19/176 ,  H04N19/597 ,  H04N19/70

Abstract: A video encoder signals, in a bitstream, a syntax element that indicates whether a current video unit is predicted from a VSP picture. The current video unit is a macroblock or a macroblock partition. The video encoder determines, based at least in part on whether the current video unit is predicted from the VSP picture, whether to signal, in the bitstream, motion information for the current video unit. A video decoder decodes the syntax element from the bitstream and determines, based at least in part on the syntax element, whether the bitstream includes the motion information.

Abstract translation: 视频编码器在比特流中发信号，指示是否从VSP图像预测当前视频单元。 当前视频单元是宏块或宏块分区。 视频编码器至少部分地基于从VSP图像预测当前视频单元，确定在比特流中是否向当前视频单元发送运动信息。 视频解码器从比特流解码语法元素，并且至少部分地基于语法元素确定比特流是否包括运动信息。

公开(公告)号：US20230394738A1

公开(公告)日：2023-12-07

申请号：US18035507

申请日：2020-11-09

Applicant: QUALCOMM Incorporated

Inventor： Yibin ZHANG ,  Zilin YING ,  Yun DU ,  Heng QI ,  Jiexia YU ,  Yang YU ,  Andrew Evan GRUBER ,  Jian LIANG ,  Tao WANG ,  Alexei Vladimirovich BOURD ,  Gang ZHONG ,  Minjie HUANG

IPC: G06T15/00

CPC classification number: G06T15/005

Abstract: The present disclosure relates to methods and apparatus for graphics processing, e.g., a GPU. The apparatus may receive an image including a plurality of pixels associated with one or more workgroups and one or more pixel tiles, each of the workgroups and the pixel tiles including one or more pixels of the plurality of pixels. The apparatus may determine whether the one or more workgroups are misaligned with the one or more pixel tiles. The apparatus may determine a conversion order of the one or more workgroups when the one or more workgroups are misaligned with the one or more pixel tiles, the conversion order corresponding to a common multiple of one of the one or more workgroups and one of the one or more pixel tiles. The apparatus may convert each of the one or more workgroups based on the conversion order of the one or more workgroups.

公开(公告)号：US20150264400A1

公开(公告)日：2015-09-17

申请号：US14216369

申请日：2014-03-17

Applicant: QUALCOMM Incorporated

Inventor： In Suk CHONG ,  Yang YU ,  Xianglin WANG ,  Marta KARCZEWICZ

IPC: H04N19/60 ,  H04N19/42

CPC classification number: H04N19/60 ,  H04N19/42

Abstract: Systems and methods for low complexity forward transforms using mesh-based calculations are described herein. One aspect of the subject matter described in the disclosure provides a video encoder comprising a memory configured to store video information. The video encoder further comprises a processor in communication with the memory. The processor is configured to decompose a transform into multiple transform stages. The processor is further configured to transform the video information using the multiple stages to determine a transform stage output at each transform stage. The processor is further configured to constrain the transform stage output at each transform stage to a predetermined bit depth. The processor is further configured to perform operations on the constrained transform output of a last stage of the multiple stages, wherein the operations are only available for use with data having the predetermined bit depth.

Abstract translation: 本文描述了使用基于网格的计算的低复杂度正向变换的系统和方法。 在本公开中描述的主题的一个方面提供了一种视频编码器，其包括被配置为存储视频信息的存储器。 视频编码器还包括与存储器通信的处理器。 处理器被配置为将变换分解成多个变换阶段。 处理器还被配置为使用多级转换视频信息，以确定在每个变换阶段的变换级输出。 处理器还被配置为将每个变换级的变换级输出约束到预定位深度。 处理器还被配置为对多级的最后阶段的约束变换输出执行操作，其中该操作仅可用于具有预定位深度的数据。

公开(公告)号：US20230082420A1

公开(公告)日：2023-03-16

申请号：US17473691

申请日：2021-09-13

Applicant: QUALCOMM Incorporated

Inventor： Yang YU ,  Scott BARKER ,  Jonathan KIES

IPC: G09G3/00 ,  G06T7/73 ,  G06F3/0346 ,  G06T7/60

Abstract: Systems and techniques are described herein for displaying digital media content (e.g., electronic books) on physical surfaces or objects. The systems and techniques can be implemented by various types of systems, such as by an extended reality (XR) system or device. For example, a process can include receiving, by an extended reality device, a request to display media content on a display surface. The process can include determining a pose of the display surface and a pose of the extended reality device. The process can include, based on the pose of the display surface and the pose of the extended reality device, displaying the media content by the extended reality device relative to the display surface.

公开(公告)号：US20220357983A1

公开(公告)日：2022-11-10

申请号：US17315205

申请日：2021-05-07

Applicant: QUALCOMM Incorporated

Inventor： Yun DU ,  Andrew Evan GRUBER ,  Zilin YING ,  Gang ZHONG ,  Baoguang YANG ,  Yang YU ,  Yang XIA ,  Ravindra KUMAR ,  Chun YU ,  Eric DEMERS

IPC: G06F9/48 ,  G06F12/0875 ,  G06T1/20

Abstract: The present disclosure relates to methods and devices for graphics processing including an apparatus, e.g., a GPU. The apparatus may receive a plurality of workloads based on a workload order, each of the plurality of workloads being received in the workload order including at least a first workload and a second workload. The apparatus may also allocate one or more workloads of the plurality of workloads to one or more wave slots. Additionally, the apparatus may execute the one or more allocated workloads at the one or more wave slots, such that at least the first workload is executed at the first wave slot and the second workload is executed at the second wave slot. The apparatus may also allocate at least one other workload of the plurality of workloads to at least one previously-allocated wave slot of the one or more wave slots.

公开(公告)号：US20150264403A1

公开(公告)日：2015-09-17

申请号：US14216086

申请日：2014-03-17

Applicant: QUALCOMM INCORPORATED

Inventor： In Suk CHONG ,  Yang YU ,  Xianglin WANG ,  Marta KARCZEWICZ

IPC: H04N19/61 ,  H04N19/186 ,  H04N19/182 ,  H04N19/176 ,  H04N19/18

CPC classification number: H04N19/61 ,  H04N19/122 ,  H04N19/132 ,  H04N19/14 ,  H04N19/176 ,  H04N19/18

Abstract: Systems and methods for low complexity forward transforms using zeroed-out coefficients are described herein. One aspect of the subject matter described in the disclosure provides a video encoder comprising a memory configured to store a video block. The video encoder further comprises a processor in communication with the memory. The processor is configured to determine a full power value of the video block. The processor is further configured to determine a reduced transform coefficient matrix, wherein the reduced transform coefficient matrix comprises an inner region of zero or non-zero values of the same inner region of a full transform coefficient matrix and an outer region of zero values, wherein the reduced transform coefficient matrix and the full transform coefficient matrix have the same size. The processor is further configured to determine a partial power value of the video block using the reduced transform coefficient matrix. The processor is further configured to transform the video block from a pixel domain to a coefficient domain using the reduced transform coefficient matrix based on the full power value and partial power value. The processor is further configured to encode the transformed video block.

Abstract translation: 本文描述了使用零缺失系数的低复杂度正向变换的系统和方法。 在本公开中描述的主题的一个方面提供了一种视频编码器，其包括被配置为存储视频块的存储器。 视频编码器还包括与存储器通信的处理器。 处理器被配置为确定视频块的全功率值。 处理器还被配置为确定缩小的变换系数矩阵，其中所述经简化的变换系数矩阵包括全变换系数矩阵和零值的外部区域的相同内部区域的零或非零值的内部区域，其中 减小的变换系数矩阵和全变换系数矩阵具有相同的大小。 处理器还被配置为使用缩减的变换系数矩阵来确定视频块的部分功率值。 处理器还被配置为使用基于全功率值和部分功率值的减小的变换系数矩阵将视频块从像素域变换到系数域。 处理器还被配置为对经变换的视频块进行编码。