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公开(公告)号：US20240370967A1
公开(公告)日：2024-11-07
申请号：US18777430
申请日：2024-07-18
Applicant: QUALCOMM Incorporated
Inventor： Kalyan Kumar BHIRAVABHATLA , Andrew Evan GRUBER , Rahul Sunil KUKREJA , Vishwanath Shashikant NIKAM , Tao WANG , Jian LIANG
Abstract: This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for improving visibility generation in tile-based GPU architectures. A graphics processor may perform a first binning pass associated with visibility information for each of a plurality of primitives in at least one frame. The visibility information for each of the plurality of primitives may correspond to a visible indication or an invisible indication. The graphics processor may update a depth buffer based on the visibility information for all of the plurality of primitives in the at least one frame. The graphics processor may perform a second binning pass for each of the visible set of primitives based on the updated depth buffer. The graphics processor may store at least one of the updated visibility information or updated position data for all primitives in the visible set of primitives from the second binning pass.
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公开(公告)号：US20240104684A1
公开(公告)日：2024-03-28
申请号：US17935031
申请日：2022-09-23
Applicant: QUALCOMM Incorporated
Inventor： Kalyan Kumar BHIRAVABHATLA , Andrew Evan GRUBER , Rahul Sunil KUKREJA , Vishwanath Shashikant NIKAM , Tao WANG , Jian LIANG
Abstract: This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for improving visibility generation in tile-based GPU architectures. A graphics processor may perform a first binning pass associated with visibility information for each of a plurality of primitives in at least one frame. The visibility information for each of the plurality of primitives may correspond to a visible indication or an invisible indication. The graphics processor may update a depth buffer based on the visibility information for all of the plurality of primitives in the at least one frame. The graphics processor may perform a second binning pass for each of the visible set of primitives based on the updated depth buffer. The graphics processor may store at least one of the updated visibility information or updated position data for all primitives in the visible set of primitives from the second binning pass.
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公开(公告)号：US20230394738A1
公开(公告)日：2023-12-07
申请号：US18035507
申请日：2020-11-09
Applicant: QUALCOMM Incorporated
Inventor： Yibin ZHANG , Zilin YING , Yun DU , Heng QI , Jiexia YU , Yang YU , Andrew Evan GRUBER , Jian LIANG , Tao WANG , Alexei Vladimirovich BOURD , Gang ZHONG , Minjie HUANG
IPC: G06T15/00
CPC classification number: G06T15/005
Abstract: The present disclosure relates to methods and apparatus for graphics processing, e.g., a GPU. The apparatus may receive an image including a plurality of pixels associated with one or more workgroups and one or more pixel tiles, each of the workgroups and the pixel tiles including one or more pixels of the plurality of pixels. The apparatus may determine whether the one or more workgroups are misaligned with the one or more pixel tiles. The apparatus may determine a conversion order of the one or more workgroups when the one or more workgroups are misaligned with the one or more pixel tiles, the conversion order corresponding to a common multiple of one of the one or more workgroups and one of the one or more pixel tiles. The apparatus may convert each of the one or more workgroups based on the conversion order of the one or more workgroups.
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公开(公告)号：US20200020067A1
公开(公告)日：2020-01-16
申请号：US16035372
申请日：2018-07-13
Applicant: QUALCOMM Incorporated
Inventor： Jian LIANG , Tao WANG , Chun YU , Andrew Evan GRUBER , Donghyun KIM , Nigel POOLE , Tzun-Wei LEE , Shambhoo KHANDELWAL
Abstract: A method, an apparatus, and a computer-readable medium may be configured to perform a binning pass for a first frame. The apparatus may be configured to perform a rendering pass for the first frame in parallel with the binning pass. The apparatus may be configured to enhance efficiency in performing a binning pass and a rendering pass for tile-based rendering, such that the binning pass and rendering pass are performed concurrently. The apparatus may be configured to perform the binning pass using a first hardware pipeline, and may be configured to perform the rendering pass using a second hardware pipeline.
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公开(公告)号：US20170031785A1
公开(公告)日：2017-02-02
申请号：US15170742
申请日：2016-06-01
Applicant: QUALCOMM Incorporated
Inventor： Edwin JOSE , Tao WANG
CPC classification number: G06F11/1471 , G06F3/0619 , G06F3/0632 , G06F3/0679 , G06F13/1668 , G06F2201/805 , G06F2201/84 , G06F2201/85
Abstract: Some aspects of the disclosure include a self-refresh entry sequence for a memory, such as a DRAM, that may be used to avoid a frequency mismatch between a system processor and a system memory. The self-refresh entry sequence may signal the memory to reset the frequency set point state and default to the power-up state upon a self-refresh process exit. In another aspect, a new mode register may be used to indicate that the frequency set point needs to be reset after the next self-refresh entry command. In this aspect, the processor will execute a mode register write command followed by a self-refresh entry in response to the occurrence of a crash event. Then, the memory will reset to the default frequency set point by the end of self-refresh entry execution.
Abstract translation: 本公开的一些方面包括用于诸如DRAM的存储器的自刷新入口序列，其可以用于避免系统处理器和系统存储器之间的频率不匹配。 自刷新入口序列可能会在存储器中发信号通知复位频率设定点状态，并在自刷新过程退出时默认为上电状态。 另一方面，可以使用新的模式寄存器来指示频率设定点需要在下一个自刷新输入命令之后复位。 在这方面，处理器将执行模式寄存器写入命令，随后响应于碰撞事件的发生而进行自刷新条目。 然后，在自刷新输入执行结束时，存储器将重置为默认频率设定点。
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Patent Agency Ranking
公开(公告)号：US20240265486A1
公开(公告)日：2024-08-08
申请号：US18163845
申请日：2023-02-02
Applicant: QUALCOMM Incorporated
Inventor： Tao WANG , Ashokanand NEELAMBARAN , Jian LIANG , Xiayang ZHAO , Lingjun CHEN
Abstract: This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for backface culling for guard band clipping primitives. A graphics processor may identify at least one backface primitive in a set of primitives that extends beyond at least one guard band, where the at least one backface primitive is identified based on a set of fixed point coordinates. The graphics processor may cull the at least one backface primitive. The graphics processor may transmit an indication of the culled at least one backface primitive.
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公开(公告)号：US20250086882A1
公开(公告)日：2025-03-13
申请号：US18465103
申请日：2023-09-11
Applicant: QUALCOMM Incorporated
Inventor： Tao WANG , Xiayang ZHAO , Huaibing ZHU , Ruohong ZHOU , Jian LIANG , Junmei SHAO , Qinyu CHEN
Abstract: Aspects presented herein relate to methods and devices for graphics processing including an apparatus, e.g., GPU. The apparatus may obtain an indication of a set of primitives for a draw call operation. The apparatus may also identify a subset of primitives in the set of primitives, each of the subset of primitives including a primitive portion that is outside of a viewing frustum for the draw call operation, and the primitive portion corresponding to less than all of each of the subset of primitives. Further, the apparatus may calculate an area of each of the subset of primitives including the primitive portion that is outside of the viewing frustum. The apparatus may also perform, or refrain from performing, a clipping operation for each of the subset of primitives based on the area of each of the subset of primitives being less than or greater than an area threshold.
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公开(公告)号：US20250069181A1
公开(公告)日：2025-02-27
申请号：US18456083
申请日：2023-08-25
Applicant: QUALCOMM Incorporated
Abstract: Aspects of the disclosure are directed to information processing. In accordance with one aspect, information processing includes a databus; a memory system coupled to the databus; and a graphics processing unit (GPU) coupled to the memory system and the databus, wherein the GPU is configured to do the following: retrieve a first plurality of atomic operations containing a first plurality of data values for a shared memory location; compute a first aggregate data value based on the first plurality of data values; and generate a first aggregate atomic operation containing the first aggregate data value.
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公开(公告)号：US20240205433A1
公开(公告)日：2024-06-20
申请号：US18066087
申请日：2022-12-14
Applicant: QUALCOMM Incorporated
Inventor： Hyung Joon KIM , Wei-Jung CHIEN , Cheng-Teh HSIEH , Marta KARCZEWICZ , Natan JACOBSON , Tao WANG , Clara Ka Wah SUNG , Andrew Edmund TURNER
IPC: H04N19/34 , H04N19/124 , H04N19/60
CPC classification number: H04N19/34 , H04N19/124 , H04N19/60
Abstract: This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for truncation error signaling and adaptive dither for lossy bandwidth compression. A processor may perform a truncation process for data, where the data is associated with display processing, image processing, or the data processing, where the truncation process for the data results in truncated data. The processor may compute a set of truncation error values associated with the truncation process for the truncated data. The processor may generate a set of residual samples for the truncated data. The processor may generate a bitstream based on the set of residual samples for the truncated data and the set of truncation error values associated with the truncation process.
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公开(公告)号：US20230092394A1
公开(公告)日：2023-03-23
申请号：US17478694
申请日：2021-09-17
Applicant: QUALCOMM Incorporated
Inventor： Ashokanand NEELAMBARAN , Piyush GUPTA , Kalyan Kumar BHIRAVABHATLA , Tao WANG , Andrew Evan GRUBER
IPC: G06T1/20 , G06T11/40 , G06T3/40 , A63F13/525
Abstract: Aspects presented herein relate to methods and devices for graphics processing including an apparatus, e.g., a GPU. The apparatus may receive a plurality of primitives associated with one or more frames in a scene, a portion of the scene being associated with an upscaled sample space and/or a downscaled sample space. The apparatus may also perform a binning pass for the plurality of primitives, the binning pass being associated with an unscaled sample space, where the binning pass sorts each of the primitives into one or more bins associated with each of the one or more frames. Further, the apparatus may perform one of one or more rendering passes for each of the one or more bins. The apparatus may also rasterize each of the plurality of primitives based on at least one of the upscaled sample space or the downscaled sample space.
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