公开(公告)号：US20240311207A1

公开(公告)日：2024-09-19

申请号：US18184381

申请日：2023-03-15

Applicant: QUALCOMM Incorporated

Inventor： Jian LIANG ,  Hu YI ,  Tao WANG ,  Fei XU ,  Ruobai FENG

IPC: G06F9/50 ,  G06F9/54

CPC classification number: G06F9/5077 ,  G06F9/5038 ,  G06F9/5083 ,  G06F9/544

Abstract: Aspects of the disclosure are directed to coordination. In accordance with one aspect, an apparatus including a plurality of slices, wherein each slice of the plurality of slices is configured for distributed information processing; and a plurality of dedicated databuses, wherein each slice of the plurality of slices is coupled to one of the plurality of dedicated databuses and each slice of the plurality of slices is configured for local coordination for the distributed information processing.

公开(公告)号：US20240078737A1

公开(公告)日：2024-03-07

申请号：US18320792

申请日：2023-05-19

Applicant: QUALCOMM Incorporated

Inventor： Jian LIANG ,  Andrew Evan GRUBER ,  Tao WANG ,  Xuefeng TANG ,  Vishwanath Shashikant NIKAM ,  Nigel POOLE ,  Kalyan Kumar BHIRAVABHATLA ,  Fei XU ,  Zilin YING

IPC: G06T15/00

CPC classification number: G06T15/005

Abstract: A sliced graphics processing unit (GPU) architecture in processor-based devices is disclosed. In some aspects, a GPU based on a sliced GPU architecture includes multiple hardware slices. The GPU further includes a command processor (CP) circuit and an unslice primitive controller (PC_US). Upon receiving a graphics instruction from a central processing unit (CPU), the CP circuit determines a graphics workload, and transmits the graphics workload to the PC_US. The PC_US then partitions the graphics workload into multiple subbatches and distributes each subbatch to a PC_S of a hardware slice for processing.

公开(公告)号：US20250069181A1

公开(公告)日：2025-02-27

申请号：US18456083

申请日：2023-08-25

Applicant: QUALCOMM Incorporated

Inventor： Tao WANG ,  Jing HAN ,  Yun LI ,  Fei XU

IPC: G06T1/20 ,  G06F9/48 ,  G06T1/60

Abstract: Aspects of the disclosure are directed to information processing. In accordance with one aspect, information processing includes a databus; a memory system coupled to the databus; and a graphics processing unit (GPU) coupled to the memory system and the databus, wherein the GPU is configured to do the following: retrieve a first plurality of atomic operations containing a first plurality of data values for a shared memory location; compute a first aggregate data value based on the first plurality of data values; and generate a first aggregate atomic operation containing the first aggregate data value.