公开(公告)号：US20200020067A1

公开(公告)日：2020-01-16

申请号：US16035372

申请日：2018-07-13

Applicant: QUALCOMM Incorporated

Inventor： Jian LIANG ,  Tao WANG ,  Chun YU ,  Andrew Evan GRUBER ,  Donghyun KIM ,  Nigel POOLE ,  Tzun-Wei LEE ,  Shambhoo KHANDELWAL

IPC: G06T1/20 ,  G06T15/00 ,  G06T1/60

Abstract: A method, an apparatus, and a computer-readable medium may be configured to perform a binning pass for a first frame. The apparatus may be configured to perform a rendering pass for the first frame in parallel with the binning pass. The apparatus may be configured to enhance efficiency in performing a binning pass and a rendering pass for tile-based rendering, such that the binning pass and rendering pass are performed concurrently. The apparatus may be configured to perform the binning pass using a first hardware pipeline, and may be configured to perform the rendering pass using a second hardware pipeline.

公开(公告)号：US20200210299A1

公开(公告)日：2020-07-02

申请号：US16815718

申请日：2020-03-11

Applicant: QUALCOMM Incorporated

Inventor： Rahul GULATI ,  Andrew Evan GRUBER ,  Brendon Lewis JOHNSON ,  Jay Chunsup YUN ,  Donghyun KIM ,  Alex Kwang Ho JONG ,  Anshuman SAXENA

IPC: G06F11/22 ,  G06T1/20 ,  G06T15/00 ,  G06F11/07 ,  G01R31/317 ,  G01R31/3187 ,  G06F11/277

Abstract: The disclosure describes techniques for a self-test of a graphics processing unit (GPU) independent of instructions from another processing device. The GPU may perform the self-test in response to a determination that the GPU enters an idle mode. The self-test may be based on information indicating a safety level, where the safety level indicates how many faults in circuits or memory blocks of the GPU need to be detected.

公开(公告)号：US20240104837A1

公开(公告)日：2024-03-28

申请号：US18447155

申请日：2023-08-09

Applicant: QUALCOMM Incorporated

Inventor： Vineet GOEL ,  Andrew Evan GRUBER ,  Donghyun KIM

IPC: G06T15/80 ,  G06T15/00

CPC classification number: G06T15/80 ,  G06T15/00 ,  G06T15/005 ,  G06T17/20

Abstract: Aspects of this disclosure relate to a process for rendering graphics that includes performing, with a hardware unit of a graphics processing unit (GPU) designated for vertex shading, a vertex shading operation to shade input vertices so as to output vertex shaded vertices, wherein the hardware unit adheres to an interface that receives a single vertex as an input and generates a single vertex as an output. The process also includes performing, with the hardware unit of the GPU designated for vertex shading, a hull shading operation to generate one or more control points based on one or more of the vertex shaded vertices, wherein the one or more hull shading operations operate on at least one of the one or more vertex shaded vertices to output the one or more control points.

公开(公告)号：US20200311859A1

公开(公告)日：2020-10-01

申请号：US16368782

申请日：2019-03-28

Applicant: QUALCOMM Incorporated

Inventor： Yun DU ,  Nigel POOLE ,  Zilin YING ,  Ling Feng HUANG ,  Donghyun KIM ,  Chun YU ,  Tzun-Wei LEE ,  Xuefeng TANG ,  Shambhoo KHANDELWAL ,  Hongjiang SHANG ,  Elina KAMENETSKAYA ,  Zhu LIANG ,  Cary ROBINS

IPC: G06T1/20 ,  G06F9/48

Abstract: The present disclosure relates to methods and apparatus for graphics processing. In some aspects, multiple processing units can be in a graphics processing pipeline of a GPU. The apparatus can also group the multiple processing units into one or more processing unit clusters. In some aspects, each of the one or more processing unit clusters can correspond to one or more context registers. Additionally, the apparatus can determine one or more context states of the one or more context registers in each of the one or more processing unit clusters. Also, the apparatus can implement one or more execution counters corresponding to at least one of the one or more processing unit clusters in the graphics processing pipeline, where each of the one or more execution counters includes an execution value.