公开(公告)号：US20210120248A1

公开(公告)日：2021-04-22

申请号：US17104353

申请日：2020-11-25

Applicant: QUALCOMM Incorporated

Inventor： In Suk CHONG ,  Xianglin WANG ,  Cheng-Teh HSIEH

IPC: H04N19/13 ,  H03M7/30 ,  G06N3/02 ,  H04L29/06 ,  H04N19/176

Abstract: Techniques and systems are provided for compressing data in a neural network. For example, output data can be obtained from a node of the neural network. Re-arranged output data having a re-arranged scanning pattern can be generated. The re-arranged output data can be generated by re-arranging the output data into the re-arranged scanning pattern. One or more residual values can be determined for the re-arranged output data by applying a prediction mode to the re-arranged output data. The one or more residual values can then be compressed using a coding mode.

公开(公告)号：US20150264403A1

公开(公告)日：2015-09-17

申请号：US14216086

申请日：2014-03-17

Applicant: QUALCOMM INCORPORATED

Inventor： In Suk CHONG ,  Yang YU ,  Xianglin WANG ,  Marta KARCZEWICZ

IPC: H04N19/61 ,  H04N19/186 ,  H04N19/182 ,  H04N19/176 ,  H04N19/18

CPC classification number: H04N19/61 ,  H04N19/122 ,  H04N19/132 ,  H04N19/14 ,  H04N19/176 ,  H04N19/18

Abstract: Systems and methods for low complexity forward transforms using zeroed-out coefficients are described herein. One aspect of the subject matter described in the disclosure provides a video encoder comprising a memory configured to store a video block. The video encoder further comprises a processor in communication with the memory. The processor is configured to determine a full power value of the video block. The processor is further configured to determine a reduced transform coefficient matrix, wherein the reduced transform coefficient matrix comprises an inner region of zero or non-zero values of the same inner region of a full transform coefficient matrix and an outer region of zero values, wherein the reduced transform coefficient matrix and the full transform coefficient matrix have the same size. The processor is further configured to determine a partial power value of the video block using the reduced transform coefficient matrix. The processor is further configured to transform the video block from a pixel domain to a coefficient domain using the reduced transform coefficient matrix based on the full power value and partial power value. The processor is further configured to encode the transformed video block.

Abstract translation: 本文描述了使用零缺失系数的低复杂度正向变换的系统和方法。 在本公开中描述的主题的一个方面提供了一种视频编码器，其包括被配置为存储视频块的存储器。 视频编码器还包括与存储器通信的处理器。 处理器被配置为确定视频块的全功率值。 处理器还被配置为确定缩小的变换系数矩阵，其中所述经简化的变换系数矩阵包括全变换系数矩阵和零值的外部区域的相同内部区域的零或非零值的内部区域，其中 减小的变换系数矩阵和全变换系数矩阵具有相同的大小。 处理器还被配置为使用缩减的变换系数矩阵来确定视频块的部分功率值。 处理器还被配置为使用基于全功率值和部分功率值的减小的变换系数矩阵将视频块从像素域变换到系数域。 处理器还被配置为对经变换的视频块进行编码。

公开(公告)号：US20130336382A1

公开(公告)日：2013-12-19

申请号：US13767676

申请日：2013-02-14

Applicant: QUALCOMM INCORPORATED

Inventor： Joel SOLE ROJALS ,  In Suk CHONG ,  Marta KARCZEWICZ

IPC: H04N7/26

CPC classification number: H04N19/136 ,  H04N19/13 ,  H04N19/184 ,  H04N19/70 ,  H04N19/82

Abstract: A video encoder generates a sequence of sample adaptive offset (SAO) syntax elements for a coding tree block. The SAO syntax elements include regular context-adaptive binary arithmetic coding (CABAC) coded bins for a color component and bypass-coded bins for the color component. None of the bypass-coded bins is between two of the regular CABAC-coded bins in the sequence. The video encoder uses regular CABAC to encode the regular CABAC-coded bins and uses bypass coding to encode the bypass-coded bins. The video encoder outputs the SAO syntax elements in a bitstream. A video decoder receives the bitstream, uses regular CABAC to decode the regular CABAC-coded bins, uses bypass coding to decode the bypass-coded bins, and modifies a reconstructed picture based on the SAO syntax elements.

Abstract translation: 视频编码器生成用于编码树块的采样自适应偏移（SAO）语法元素的序列。 SAO语法元素包括用于颜色分量的常规上下文自适应二进制算术编码（CABAC）编码箱和用于颜色分量的旁路编码箱。 没有一个旁路编码的存储区位于序列中的两个常规CABAC编码区间之间。 视频编码器使用常规CABAC对常规CABAC编码的存储区进行编码，并使用旁路编码对旁路编码的存储区进行编码。 视频编码器输出比特流中的SAO语法元素。 视频解码器接收比特流，使用常规CABAC来解码常规CABAC编码箱，使用旁路编码来解码旁路编码箱，并且基于SAO语法元素修改重构图像。

公开(公告)号：US20200098138A1

公开(公告)日：2020-03-26

申请号：US16140108

申请日：2018-09-24

Applicant: QUALCOMM Incorporated

Inventor： In Suk CHONG ,  Xianglin WANG ,  Cheng-Teh HSIEH

IPC: G06T9/00 ,  H03M7/24 ,  G06F7/483 ,  H04N19/124 ,  H04N19/182

Abstract: Certain aspects of the present disclosure provide a method of encoding data. The method generally includes receiving data comprising a fractional number comprising an exponential component and a fractional component, the exponential component being represented by an exponential bit sequence, the fractional component being represented by a fractional bit sequence. The method further includes determining if the fractional component is within a threshold of 0 or 1. The method further includes setting the fractional component to 0 when the fractional component is within the threshold of 0 or 1. The method further includes downscaling the fractional bit sequence based on a difference between the exponential component and a second threshold. The method further includes encoding the data. The method further includes transmitting the encoded data.

公开(公告)号：US20190373264A1

公开(公告)日：2019-12-05

申请号：US15991685

申请日：2018-05-29

Applicant: QUALCOMM Incorporated

Inventor： In Suk CHONG ,  Xianglin WANG ,  Cheng-Teh HSIEH

IPC: H04N19/13 ,  H03M7/30 ,  H04N19/176 ,  H04L29/06 ,  G06N3/02

Abstract: Techniques and systems are provided for compressing data in a neural network. For example, output data can be obtained from a node of the neural network. Re-arranged output data having a re-arranged scanning pattern can be generated. The re-arranged output data can be generated by re-arranging the output data into the re-arranged scanning pattern. One or more residual values can be determined for the re-arranged output data by applying a prediction mode to the re-arranged output data. The one or more residual values can then be compressed using a coding mode.

公开(公告)号：US20150264400A1

公开(公告)日：2015-09-17

申请号：US14216369

申请日：2014-03-17

Applicant: QUALCOMM Incorporated

Inventor： In Suk CHONG ,  Yang YU ,  Xianglin WANG ,  Marta KARCZEWICZ

IPC: H04N19/60 ,  H04N19/42

CPC classification number: H04N19/60 ,  H04N19/42

Abstract: Systems and methods for low complexity forward transforms using mesh-based calculations are described herein. One aspect of the subject matter described in the disclosure provides a video encoder comprising a memory configured to store video information. The video encoder further comprises a processor in communication with the memory. The processor is configured to decompose a transform into multiple transform stages. The processor is further configured to transform the video information using the multiple stages to determine a transform stage output at each transform stage. The processor is further configured to constrain the transform stage output at each transform stage to a predetermined bit depth. The processor is further configured to perform operations on the constrained transform output of a last stage of the multiple stages, wherein the operations are only available for use with data having the predetermined bit depth.

Abstract translation: 本文描述了使用基于网格的计算的低复杂度正向变换的系统和方法。 在本公开中描述的主题的一个方面提供了一种视频编码器，其包括被配置为存储视频信息的存储器。 视频编码器还包括与存储器通信的处理器。 处理器被配置为将变换分解成多个变换阶段。 处理器还被配置为使用多级转换视频信息，以确定在每个变换阶段的变换级输出。 处理器还被配置为将每个变换级的变换级输出约束到预定位深度。 处理器还被配置为对多级的最后阶段的约束变换输出执行操作，其中该操作仅可用于具有预定位深度的数据。

公开(公告)号：US20150264367A1

公开(公告)日：2015-09-17

申请号：US14216205

申请日：2014-03-17

Applicant: QUALCOMM Incorporated

Inventor： In Suk CHONG ,  Sungwon Lee ,  Xianglin Wang ,  Marta Karczewicz

IPC: H04N19/23 ,  H04N19/174

CPC classification number: H04N19/23 ,  H04N19/103 ,  H04N19/137 ,  H04N19/174 ,  H04N19/176 ,  H04N19/557

Abstract: Systems and methods for low complexity encoding and background detection are described herein. One aspect of the subject matter described in the disclosure provides a video encoder comprising a memory configured to store a video block. The video encoder further comprises a processor in communication with the memory. The processor is configured to determine whether the video block is background by comparing the video block to a corresponding block located in a previous temporal frame. The processor is further configured to determine, when the video block is not background, whether one or more sub-blocks of the video block are background by comparing the sub-blocks to corresponding sub-blocks located in the previous temporal frame.

Abstract translation: 本文描述了用于低复杂度编码和背景检测的系统和方法。 在本公开中描述的主题的一个方面提供了一种视频编码器，其包括被配置为存储视频块的存储器。 视频编码器还包括与存储器通信的处理器。 处理器被配置为通过将视频块与位于先前时间帧中的对应块进行比较来确定视频块是否是背景。 处理器还被配置为通过将子块与位于先前时间帧中的对应子块进行比较来确定何时视频块不是背景，视频块的一个或多个子块是否是背景。