公开(公告)号：US10956645B2

公开(公告)日：2021-03-23

申请号：US16366918

申请日：2019-03-27

Applicant: QUALCOMM Incorporated

Inventor： Joon Hyung Chung ,  Mikhail Popovich ,  Gudoor Reddy

IPC: H01L29/40 ,  H01L23/52 ,  H01L23/48 ,  G06F30/394 ,  G06F30/39 ,  G06F30/327 ,  G06F30/392 ,  G06F30/398 ,  H01L23/522 ,  H01L23/528 ,  G06F115/08 ,  G06F119/06

Abstract: The place and route stage for a hard macro is modified to assign a more robust power-grid tier to a critical path for a hard macro and to assign a less robust power-grid tier to a remainder of the hard macro.

公开(公告)号：US20180144086A1

公开(公告)日：2018-05-24

申请号：US15432431

申请日：2017-02-14

Applicant: QUALCOMM Incorporated

Inventor： Joon Hyung Chung ,  Mikhail Popovich ,  Gudoor Reddy

IPC: G06F17/50 ,  H01L23/528 ,  H01L23/522

CPC classification number: G06F17/5077 ,  G06F17/505 ,  G06F17/5068 ,  G06F17/5072 ,  G06F17/5081 ,  G06F2217/66 ,  G06F2217/78 ,  H01L23/5226 ,  H01L23/5286

Abstract: The place and route stage for a hard macro including a plurality of tiles is modified so that some of the tiles are assigned a more robust power-grid tier and so that others ones of the tiles are assigned a less robust power-grid tier.

公开(公告)号：US20130285696A1

公开(公告)日：2013-10-31

申请号：US13928424

申请日：2013-06-27

Applicant: QUALCOMM Incorporated

Inventor： Lew Chua-Eoan ,  Boris Andreev ,  Yuancheng Christopher Pan ,  Amirali Shayan ,  Xiaohua Kong ,  Mikhail Popovich ,  Mauricio Calle ,  IK-Joon Chang

IPC: G01R31/317

CPC classification number: G01R31/31721 ,  G01R29/26

Abstract: An on-chip sensor measures dynamic power supply noise, such as voltage droop, on a semiconductor chip. In-situ logic is employed, which is sensitive to noise present on the power supply of functional logic of the chip. Exemplary functional logic includes a microprocessor, adder, and/or other functional logic of the chip. The in-situ logic performs some operation, and the amount of time required for performing that operation (i.e., the operational delay) is sensitive to noise present on the power supply. Thus, by evaluating the operational delay of the in-situ logic, the amount of noise present on the power supply can be measured.

Abstract translation: 片上传感器测量半导体芯片上的动态电源噪声，如电压下降。 采用原位逻辑，对芯片功能逻辑电源上存在的噪声敏感。 示例性功能逻辑包括芯片的微处理器，加法器和/或其他功能逻辑。 原位逻辑执行一些操作，并且执行该操作所需的时间量（即，操作延迟）对电源上存在的噪声敏感。 因此，通过评估原位逻辑的操作延迟，可以测量电源上存在的噪声量。

公开(公告)号：US10664035B2

公开(公告)日：2020-05-26

申请号：US15692456

申请日：2017-08-31

Applicant: QUALCOMM Incorporated

Inventor： Mikhail Popovich ,  Juan Sebastian Ochoa Munoz

IPC: G11C5/14 ,  G06F1/32 ,  G06F1/26

Abstract: In certain aspects, an integrated circuit comprises a first circuit macro having a first power delivery network, a second circuit macro having a second power delivery network. The integrated circuit further comprises a coupling circuit couples to the first power delivery network and to the second power delivery network.

公开(公告)号：US20160266596A1

公开(公告)日：2016-09-15

申请号：US15164130

申请日：2016-05-25

Applicant: QUALCOMM Incorporated

Inventor： Ryan Michael Coutts ,  Mikhail Popovich

IPC: G05F3/02 ,  H01L23/64 ,  H01L23/00 ,  H01L49/02

CPC classification number: G05F3/02 ,  G05F1/00 ,  G06F1/3287 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/62 ,  H01L23/647 ,  H01L24/16 ,  H01L28/40 ,  H01L2224/16227 ,  H01L2924/15311 ,  Y02D10/171

Abstract: In one embodiment, an apparatus comprises a capacitor and a die. The die comprises a resistor switch coupled between a power line and the capacitor, wherein the resistor switch has an adjustable resistance, and the power line and the capacitor are both external to the die. The die also comprises a circuit configured to receive power from the power line, and a controller configured to open the resistor switch if the power line is powered down.

Abstract translation: 在一个实施例中，装置包括电容器和管芯。 管芯包括耦合在电源线和电容器之间的电阻器开关，其中电阻器开关具有可调电阻，并且电源线和电容器都在管芯外部。 芯片还包括被配置为从电力线接收电力的电路，以及配置成如果电源线断电则打开电阻器开关的控制器。

公开(公告)号：US20150293551A1

公开(公告)日：2015-10-15

申请号：US14250150

申请日：2014-04-10

Applicant: QUALCOMM Incorporated

Inventor： Ryan Michael Coutts ,  Mikhail Popovich

IPC: G05F3/02

CPC classification number: G05F3/02 ,  G05F1/00 ,  G06F1/3287 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/62 ,  H01L23/647 ,  H01L24/16 ,  H01L28/40 ,  H01L2224/16227 ,  H01L2924/15311 ,  Y02D10/171

Abstract: In one embodiment, an apparatus comprises a capacitor and a die. The die comprises a resistor switch coupled between a power line and the capacitor, wherein the resistor switch has an adjustable resistance, and the power line and the capacitor are both external to the die. The die also comprises a circuit configured to receive power from the power line.

Abstract translation: 在一个实施例中，装置包括电容器和管芯。 管芯包括耦合在电源线和电容器之间的电阻器开关，其中电阻器开关具有可调电阻，并且电源线和电容器都在管芯外部。 芯片还包括被配置为从电力线接收电力的电路。

公开(公告)号：US10078358B2

公开(公告)日：2018-09-18

申请号：US15171851

申请日：2016-06-02

Applicant: QUALCOMM Incorporated

Inventor： Juan Ochoa Munoz ,  Yuancheng Chris Pan ,  Mikhail Popovich ,  Joon Hyung Chung

IPC: G06F1/00 ,  G06F1/32

CPC classification number: G06F1/324 ,  G06F1/26 ,  G06F1/3296

Abstract: A power delivery network (PDN) including a battery, a set of regulators for generating supply voltages, and an integrated circuit (IC) including power rails configured to receive the supply voltages. The IC further includes an IC chip having a set of cores. The power rails includes a larger rail configured to provide a full range of currents, and the other smaller power rails each configured to provide lower range of currents. The IC includes multiplexers having first inputs coupled respectively to the smaller rails, second inputs coupled to the larger rail, and outputs coupled to the cores. When the smaller rail is able to supply the current needed by a core, the multiplexer is configured to couple the smaller rail to the core. When the smaller rail cannot supply the current needed by the core, the multiplexer is configured to couple the larger rail to the core.

公开(公告)号：US09871506B2

公开(公告)日：2018-01-16

申请号：US14254872

申请日：2014-04-16

Applicant: QUALCOMM Incorporated

Inventor： Ryan Michael Coutts ,  Mikhail Popovich

IPC: H02J3/14 ,  H03K17/16 ,  G06F1/28 ,  H03K19/0175 ,  H02J7/00 ,  H03K17/14 ,  H02J9/06 ,  H03K19/20 ,  G06F1/26

CPC classification number: H03K17/16 ,  G06F1/26 ,  G06F1/28 ,  H02J7/0063 ,  H02J9/061 ,  H03K17/145 ,  H03K19/0175 ,  H03K19/20

Abstract: Aspects of an integrated circuit are disclosed. The integrated circuit includes a first circuit configured to be powered by a first voltage source, a second circuit configured to be powered by a second voltage source, a decoupling capacitor, and a controller configured to switch the decoupling capacitor between the first and second voltage source.

公开(公告)号：US09377804B2

公开(公告)日：2016-06-28

申请号：US14250150

申请日：2014-04-10

Applicant: QUALCOMM Incorporated

Inventor： Ryan Michael Coutts ,  Mikhail Popovich

IPC: H01L23/02 ,  G05F3/02 ,  G05F1/00 ,  H01L23/50 ,  H01L23/64 ,  G06F1/32 ,  H01L23/62

CPC classification number: G05F3/02 ,  G05F1/00 ,  G06F1/3287 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/62 ,  H01L23/647 ,  H01L24/16 ,  H01L28/40 ,  H01L2224/16227 ,  H01L2924/15311 ,  Y02D10/171

Abstract: In one embodiment, an apparatus comprises a capacitor and a die. The die comprises a resistor switch coupled between a power line and the capacitor, wherein the resistor switch has an adjustable resistance, and the power line and the capacitor are both external to the die. The die also comprises a circuit configured to receive power from the power line.

Abstract translation: 在一个实施例中，装置包括电容器和管芯。 管芯包括耦合在电源线和电容器之间的电阻器开关，其中电阻器开关具有可调电阻，并且电源线和电容器都在管芯外部。 芯片还包括被配置为从电力线接收电力的电路。

公开(公告)号：US20190220571A1

公开(公告)日：2019-07-18

申请号：US16366918

申请日：2019-03-27

Applicant: QUALCOMM Incorporated

Inventor： Joon Hyung Chung ,  Mikhail Popovich ,  Gudoor Reddy

IPC: G06F17/50 ,  H01L23/528 ,  H01L23/522

CPC classification number: G06F17/5077 ,  G06F17/505 ,  G06F17/5068 ,  G06F17/5072 ,  G06F17/5081 ,  G06F2217/66 ,  G06F2217/78 ,  H01L23/5226 ,  H01L23/5286

Abstract: The place and route stage for a hard macro is modified to assign a more robust power-grid tier to a critical path for a hard macro and to assign a less robust power-grid tier to a remainder of the hard macro.