公开(公告)号：US09142268B2

公开(公告)日：2015-09-22

申请号：US13719881

申请日：2012-12-19

Applicant: QUALCOMM Incorporated

Inventor： Jentsung Lin ,  Paul D. Bassett ,  Manojkumar Pyla ,  Robert A. Lester ,  Christopher E. Koob

IPC: G11C7/00 ,  G11C7/10 ,  G06F5/10

CPC classification number: G11C7/1084 ,  G06F5/10

Abstract: Dual-voltage domain memory buffers, and related systems and methods are disclosed. To reduce area needed for voltage level shifters for voltage level shifting, latch banks are provided in a voltage domain of memory buffer read circuitry, separate from the voltage domain of a write data input to the latch banks. A write data input voltage level shifter is disposed between the write data input and the latch banks to voltage level shift write data on the write data input to the voltage domain of the latch banks. In this manner, voltage level shifters are not required to voltage level shill the latch bank outputs, because the latch banks are in the voltage domain of the memory buffer read circuitry. In this manner, semiconductor area that would otherwise be needed for the voltage level shifters to voltage level shift latch bank outputs is not required.

Abstract translation: 公开了双电压域内存缓冲器以及相关的系统和方法。 为了减小用于电压电平移位的电压电平移位器所需的面积，锁存器组被提供在存储缓冲器读取电路的电压域中，与写入数据输入到锁存器组的电压域分开。 写入数据输入电压电平移位器设置在写入数据输入和锁存器组之间，以输入到锁存器组的电压域的写入数据上的电压电平移位写入数据。 以这种方式，由于锁存器组处于存储器缓冲器读取电路的电压域中，电压电平移位器不需要电压电平降低锁存器组输出。 以这种方式，不需要将电压电平移位器需要的电压电平移位锁存器组输出的半导体区域。

公开(公告)号：US09124276B2

公开(公告)日：2015-09-01

申请号：US13721119

申请日：2012-12-20

Applicant: QUALCOMM Incorporated

Inventor： Jentsung Lin ,  Paul D. Bassett

IPC: G01R19/00 ,  G11C7/00 ,  H03F3/45 ,  H03L5/00 ,  G11C5/14 ,  G11C7/06 ,  G11C7/10

CPC classification number: H03L5/00 ,  G11C5/14 ,  G11C7/062 ,  G11C7/065 ,  G11C7/1057 ,  G11C7/106

Abstract: An apparatus includes a sense amplifier that has a sense amplifier differential output. The sense amplifier may be in a first power domain. The apparatus may include level shifting circuitry that has a level shifter differential output. The level shifting circuitry may be coupled to the sense amplifier differential output. The level shifting circuitry may include a first transistor and a second transistor. A first sense amplifier output of the sense amplifier differential output may be coupled to the first transistor, and a second sense amplifier output of the sense amplifier differential output may be coupled to the second transistor. The apparatus may further include a latch to store data. The latch may be coupled to the level shifter differential output. The latch is in a second power domain that is different from the first power domain.

Abstract translation: 一种装置包括具有读出放大器差分输出的读出放大器。 读出放大器可以处于第一功率域。 该装置可以包括具有电平移位器差分输出的电平移位电路。 电平移位电路可以耦合到读出放大器差分输出。 电平移位电路可以包括第一晶体管和第二晶体管。 读出放大器差分输出的第一读出放大器输出可以耦合到第一晶体管，并且读出放大器差分输出的第二读出放大器输出可以耦合到第二晶体管。 该装置还可以包括用于存储数据的锁存器。 锁存器可以耦合到电平移位器差分输出。 锁存器位于与第一电源域不同的第二电源域中。

公开(公告)号：US20130182515A1

公开(公告)日：2013-07-18

申请号：US13719881

申请日：2012-12-19

Applicant: QUALCOMM Incorporated

Inventor： Jentsung Lin ,  Paul D. Bassett ,  Manojkumar Pyla ,  Robert A. Lester ,  Christopher E. Koob

IPC: G11C7/10

CPC classification number: G11C7/1084 ,  G06F5/10

Abstract: Dual-voltage domain memory buffers, and related systems and methods are disclosed. To reduce area needed for voltage level shifters for voltage level shifting, latch banks are provided in a voltage domain of memory buffer read circuitry, separate from the voltage domain of a write data input to the latch banks. A write data input voltage level shifter is disposed between the write data input and the latch banks to voltage level shift write data on the write data input to the voltage domain of the latch banks. In this manner, voltage level shifters are not required to voltage level shill the latch bank outputs, because the latch banks are in the voltage domain of the memory buffer read circuitry. In this manner, semiconductor area that would otherwise be needed for the voltage level shifters to voltage level shift latch bank outputs is not required.

Abstract translation: 公开了双电压域内存缓冲器以及相关的系统和方法。 为了减小用于电压电平移位的电压电平移位器所需的面积，锁存器组被提供在存储缓冲器读取电路的电压域中，与写入数据输入到锁存器组的电压域分开。 写入数据输入电压电平移位器设置在写入数据输入和锁存器组之间，以输入到锁存器组的电压域的写入数据上的电压电平移位写入数据。 以这种方式，由于锁存器组处于存储器缓冲器读取电路的电压域中，电压电平移位器不需要电压电平降低锁存器组输出。 以这种方式，不需要将电压电平移位器需要的电压电平移位锁存器组输出的半导体区域。

公开(公告)号：US20160063170A1

公开(公告)日：2016-03-03

申请号：US14473898

申请日：2014-08-29

Applicant: QUALCOMM Incorporated

Inventor： Jentsung Lin ,  Paul Douglas Bassett

IPC: G06F17/50

CPC classification number: G06F17/505 ,  G06F2217/70 ,  G11C29/54 ,  G11C29/72 ,  G11C29/76 ,  G11C29/80 ,  G11C29/814 ,  G11C2029/0403

Abstract: A method includes designing, at a computer, a first version of a memory device that includes first main memory and first redundant memory. The method further includes modifying a design of the first version of the memory device to produce a second version of the memory device when an error rate associated with fabrication of the first version of the memory device is below a threshold. The second version of the memory device includes second main memory that is logically identical to the first main memory, and the second version of the memory device includes less redundant memory than the first redundant memory.

Abstract translation: 一种方法包括在计算机处设计包括第一主存储器和第一冗余存储器的存储器件的第一版本。 该方法还包括当与存储器件的第一版本的制造相关联的错误率低于阈值时修改存储器件的第一版本的设计以产生存储器件的第二版本。 存储器件的第二版本包括与第一主存储器在逻辑上相同的第二主存储器，并且存储器件的第二版本包括比第一冗余存储器少的冗余存储器。

公开(公告)号：US20140176221A1

公开(公告)日：2014-06-26

申请号：US13721119

申请日：2012-12-20

Applicant: QUALCOMM INCORPORATED

Inventor： Jentsung Lin ,  Paul D. Bassett

IPC: H03L5/00

CPC classification number: H03L5/00 ,  G11C5/14 ,  G11C7/062 ,  G11C7/065 ,  G11C7/1057 ,  G11C7/106

Abstract: An apparatus includes a sense amplifier that has a sense amplifier differential output. The sense amplifier may be in a first power domain. The apparatus may include level shifting circuitry that has a level shifter differential output. The level shifting circuitry may be coupled to the sense amplifier differential output. The level shifting circuitry may include a first transistor and a second transistor. A first sense amplifier output of the sense amplifier differential output may be coupled to the first transistor, and a second sense amplifier output of the sense amplifier differential output may be coupled to the second transistor. The apparatus may further include a latch to store data. The latch may be coupled to the level shifter differential output. The latch is in a second power domain that is different from the first power domain.

Abstract translation: 一种装置包括具有读出放大器差分输出的读出放大器。 读出放大器可以处于第一功率域。 该装置可以包括具有电平移位器差分输出的电平移位电路。 电平移位电路可以耦合到读出放大器差分输出。 电平移位电路可以包括第一晶体管和第二晶体管。 读出放大器差分输出的第一读出放大器输出可以耦合到第一晶体管，并且读出放大器差分输出的第二读出放大器输出可以耦合到第二晶体管。 该装置还可以包括用于存储数据的锁存器。 锁存器可以耦合到电平移位器差分输出。 锁存器位于与第一电源域不同的第二电源域中。

公开(公告)号：US09384825B2

公开(公告)日：2016-07-05

申请号：US14499041

申请日：2014-09-26

Applicant: QUALCOMM Incorporated

Inventor： Jentsung Lin ,  Paul Bassett ,  Suresh Venkumahanti

IPC: G11C11/00 ,  G11C11/419 ,  G11C11/412 ,  G11C8/08

CPC classification number: G11C11/419 ,  G11C8/08 ,  G11C8/16 ,  G11C11/412

Abstract: A multi-port hybrid full-swing/low-swing memory circuit in a static random access memory (SRAM) device comprises a first wordline driver that comprises a read wordline driver, a second wordline driver that comprises either a read wordline driver or a read/write wordline driver, a memory cell coupled to the first and second wordline drivers, a sense amplifier coupled to the memory cell, and a latch coupled to the memory cell. The memory circuit is capable of achieving high-speed low-swing or low-speed full-swing operations while avoiding the need for a large circuit area on an integrated circuit.

Abstract translation: 静态随机存取存储器（SRAM）装置中的多端口混合全摆幅/低摆频存储器电路包括第一字线驱动器，其包括读字线驱动器，第二字线驱动器，其包括读字线驱动器或读 写入字线驱动器，耦合到第一和第二字线驱动器的存储单元，耦合到存储器单元的读出放大器和耦合到存储器单元的锁存器。 存储电路能够实现高速低摆幅或低速全摆动操作，同时避免了集成电路上的大电路面积的需要。