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公开(公告)号：US09785601B2
公开(公告)日：2017-10-10
申请号：US15045282
申请日：2016-02-17
Applicant: QUALCOMM Incorporated
Inventor： Baker S. Mohammad , Paul D. Bassett , Martin Saint-Laurent
CPC classification number: G06F13/4077 , G06F13/4072 , G06F13/4291 , H03K3/356069 , H03K3/356113 , H03K5/15 , Y02D10/14 , Y02D10/151
Abstract: A device includes a first driver circuit coupled to a first bus line, where the first driver circuit includes a first delay element. The first delay element is configured to receive a first input signal and generate a first output signal. The first output signal transitions logic levels after a first delay period when the first input signal transitions from a logic high level to a logic low level. The first output signal transitions logic levels after a second delay period when the first input signal transitions from the logic low level to the logic high level. The first delay element includes a sense amplifier. The first driver circuit is configured to transmit the first output signal over the first bus line. The device also includes a second driver circuit configured to transmit a second output signal over a second bus line.
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公开(公告)号：US08884637B2
公开(公告)日：2014-11-11
申请号：US13900775
申请日：2013-05-23
Applicant: QUALCOMM Incorporated
Inventor： Baker S. Mohammad , Hong S. Kim , Paul D. Bassett
CPC classification number: G01R31/2642 , G11C11/41 , G11C29/12 , G11C29/50
Abstract: In a particular embodiment, a method includes receiving a testing activation signal at a controller coupled to a semiconductor device. The method further includes biasing a well of at least one transistor of the semiconductor device in response to the received testing activation signal. The bias is provided by a biasing circuit that is responsive to the controller. While the well is biased, a test of the semiconductor device is performed to generate testing data.
Abstract translation: 在特定实施例中，一种方法包括在耦合到半导体器件的控制器处接收测试激活信号。 该方法还包括响应于所接收的测试激活信号来偏置半导体器件的至少一个晶体管的阱。 该偏压由对控制器作出响应的偏置电路提供。 当井被偏置时，执行半导体器件的测试以产生测试数据。
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公开(公告)号：US09142268B2
公开(公告)日：2015-09-22
申请号：US13719881
申请日：2012-12-19
Applicant: QUALCOMM Incorporated
Inventor： Jentsung Lin , Paul D. Bassett , Manojkumar Pyla , Robert A. Lester , Christopher E. Koob
CPC classification number: G11C7/1084 , G06F5/10
Abstract: Dual-voltage domain memory buffers, and related systems and methods are disclosed. To reduce area needed for voltage level shifters for voltage level shifting, latch banks are provided in a voltage domain of memory buffer read circuitry, separate from the voltage domain of a write data input to the latch banks. A write data input voltage level shifter is disposed between the write data input and the latch banks to voltage level shift write data on the write data input to the voltage domain of the latch banks. In this manner, voltage level shifters are not required to voltage level shill the latch bank outputs, because the latch banks are in the voltage domain of the memory buffer read circuitry. In this manner, semiconductor area that would otherwise be needed for the voltage level shifters to voltage level shift latch bank outputs is not required.
Abstract translation: 公开了双电压域内存缓冲器以及相关的系统和方法。 为了减小用于电压电平移位的电压电平移位器所需的面积，锁存器组被提供在存储缓冲器读取电路的电压域中，与写入数据输入到锁存器组的电压域分开。 写入数据输入电压电平移位器设置在写入数据输入和锁存器组之间，以输入到锁存器组的电压域的写入数据上的电压电平移位写入数据。 以这种方式，由于锁存器组处于存储器缓冲器读取电路的电压域中，电压电平移位器不需要电压电平降低锁存器组输出。 以这种方式，不需要将电压电平移位器需要的电压电平移位锁存器组输出的半导体区域。
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公开(公告)号：US09124276B2
公开(公告)日：2015-09-01
申请号：US13721119
申请日：2012-12-20
Applicant: QUALCOMM Incorporated
Inventor： Jentsung Lin , Paul D. Bassett
Abstract: An apparatus includes a sense amplifier that has a sense amplifier differential output. The sense amplifier may be in a first power domain. The apparatus may include level shifting circuitry that has a level shifter differential output. The level shifting circuitry may be coupled to the sense amplifier differential output. The level shifting circuitry may include a first transistor and a second transistor. A first sense amplifier output of the sense amplifier differential output may be coupled to the first transistor, and a second sense amplifier output of the sense amplifier differential output may be coupled to the second transistor. The apparatus may further include a latch to store data. The latch may be coupled to the level shifter differential output. The latch is in a second power domain that is different from the first power domain.
Abstract translation: 一种装置包括具有读出放大器差分输出的读出放大器。 读出放大器可以处于第一功率域。 该装置可以包括具有电平移位器差分输出的电平移位电路。 电平移位电路可以耦合到读出放大器差分输出。 电平移位电路可以包括第一晶体管和第二晶体管。 读出放大器差分输出的第一读出放大器输出可以耦合到第一晶体管，并且读出放大器差分输出的第二读出放大器输出可以耦合到第二晶体管。 该装置还可以包括用于存储数据的锁存器。 锁存器可以耦合到电平移位器差分输出。 锁存器位于与第一电源域不同的第二电源域中。
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Patent Agency Ranking
公开(公告)号：US20130182515A1
公开(公告)日：2013-07-18
申请号：US13719881
申请日：2012-12-19
Applicant: QUALCOMM Incorporated
Inventor： Jentsung Lin , Paul D. Bassett , Manojkumar Pyla , Robert A. Lester , Christopher E. Koob
IPC: G11C7/10
CPC classification number: G11C7/1084 , G06F5/10
Abstract: Dual-voltage domain memory buffers, and related systems and methods are disclosed. To reduce area needed for voltage level shifters for voltage level shifting, latch banks are provided in a voltage domain of memory buffer read circuitry, separate from the voltage domain of a write data input to the latch banks. A write data input voltage level shifter is disposed between the write data input and the latch banks to voltage level shift write data on the write data input to the voltage domain of the latch banks. In this manner, voltage level shifters are not required to voltage level shill the latch bank outputs, because the latch banks are in the voltage domain of the memory buffer read circuitry. In this manner, semiconductor area that would otherwise be needed for the voltage level shifters to voltage level shift latch bank outputs is not required.
Abstract translation: 公开了双电压域内存缓冲器以及相关的系统和方法。 为了减小用于电压电平移位的电压电平移位器所需的面积，锁存器组被提供在存储缓冲器读取电路的电压域中，与写入数据输入到锁存器组的电压域分开。 写入数据输入电压电平移位器设置在写入数据输入和锁存器组之间，以输入到锁存器组的电压域的写入数据上的电压电平移位写入数据。 以这种方式，由于锁存器组处于存储器缓冲器读取电路的电压域中，电压电平移位器不需要电压电平降低锁存器组输出。 以这种方式，不需要将电压电平移位器需要的电压电平移位锁存器组输出的半导体区域。
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公开(公告)号：US20160162432A1
公开(公告)日：2016-06-09
申请号：US15045282
申请日：2016-02-17
Applicant: QUALCOMM Incorporated
Inventor： Baker S. Mohammad , Paul D. Bassett , Martin Saint-Laurent
CPC classification number: G06F13/4077 , G06F13/4072 , G06F13/4291 , H03K3/356069 , H03K3/356113 , H03K5/15 , Y02D10/14 , Y02D10/151
Abstract: A device includes a first driver circuit coupled to a first bus line, where the first driver circuit includes a first delay element. The first delay element is configured to receive a first input signal and generate a first output signal. The first output signal transitions logic levels after a first delay period when the first input signal transitions from a logic high level to a logic low level. The first output signal transitions logic levels after a second delay period when the first input signal transitions from the logic low level to the logic high level. The first delay element includes a sense amplifier. The first driver circuit is configured to transmit the first output signal over the first bus line. The device also includes a second driver circuit configured to transmit a second output signal over a second bus line.
Abstract translation: 一种装置包括耦合到第一总线的第一驱动电路，其中第一驱动电路包括第一延迟元件。 第一延迟元件被配置为接收第一输入信号并产生第一输出信号。 当第一输入信号从逻辑高电平转换到逻辑低电平时，第一输出信号在第一延迟周期之后转变逻辑电平。 当第一输入信号从逻辑低电平转换到逻辑高电平时，第一输出信号在第二延迟周期之后转变逻辑电平。 第一延迟元件包括读出放大器。 第一驱动器电路被配置为通过第一总线发送第一输出信号。 该装置还包括被配置为在第二总线上传输第二输出信号的第二驱动器电路。
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公开(公告)号：US20140176221A1
公开(公告)日：2014-06-26
申请号：US13721119
申请日：2012-12-20
Applicant: QUALCOMM INCORPORATED
Inventor： Jentsung Lin , Paul D. Bassett
IPC: H03L5/00
Abstract: An apparatus includes a sense amplifier that has a sense amplifier differential output. The sense amplifier may be in a first power domain. The apparatus may include level shifting circuitry that has a level shifter differential output. The level shifting circuitry may be coupled to the sense amplifier differential output. The level shifting circuitry may include a first transistor and a second transistor. A first sense amplifier output of the sense amplifier differential output may be coupled to the first transistor, and a second sense amplifier output of the sense amplifier differential output may be coupled to the second transistor. The apparatus may further include a latch to store data. The latch may be coupled to the level shifter differential output. The latch is in a second power domain that is different from the first power domain.
Abstract translation: 一种装置包括具有读出放大器差分输出的读出放大器。 读出放大器可以处于第一功率域。 该装置可以包括具有电平移位器差分输出的电平移位电路。 电平移位电路可以耦合到读出放大器差分输出。 电平移位电路可以包括第一晶体管和第二晶体管。 读出放大器差分输出的第一读出放大器输出可以耦合到第一晶体管，并且读出放大器差分输出的第二读出放大器输出可以耦合到第二晶体管。 该装置还可以包括用于存储数据的锁存器。 锁存器可以耦合到电平移位器差分输出。 锁存器位于与第一电源域不同的第二电源域中。
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公开(公告)号：US20140068225A1
公开(公告)日：2014-03-06
申请号：US14073190
申请日：2013-11-06
Applicant: QUALCOMM Incorporated
Inventor： Erich James Plondke , Ajay Anant Ingle , Lucian Codrescu , Paul D. Bassett
IPC: G06F12/10
CPC classification number: G06F12/1027 , G06F2212/1028 , Y02D10/13
Abstract: A particular method includes receiving at least one translation lookaside buffer (TLB) configuration indicator. The at least one TLB configuration indicator indicates a specific number of entries to be enabled at a TLB. The method further includes modifying a number of searchable entries of the TLB in response to the at least one TLB configuration indicator.
Abstract translation: 一种特定的方法包括接收至少一个翻译后备缓冲器（TLB）配置指示符。 至少一个TLB配置指示符指示将在TLB处启用的特定数量的条目。 所述方法还包括响应于所述至少一个TLB配置指示符来修改所述TLB的可搜索条目的数量。
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公开(公告)号：US20130257466A1
公开(公告)日：2013-10-03
申请号：US13900775
申请日：2013-05-23
Applicant: QUALCOMM Incorporated
Inventor： Baker S. Mohammad , Hong S. Kim , Paul D. Bassett
IPC: G01R31/26
CPC classification number: G01R31/2642 , G11C11/41 , G11C29/12 , G11C29/50
Abstract: In a particular embodiment, a method includes receiving a testing activation signal at a controller coupled to a semiconductor device. The method further includes biasing a well of at least one transistor of the semiconductor device in response to the received testing activation signal. The bias is provided by a biasing circuit that is responsive to the controller. While the well is biased, a test of the semiconductor device is performed to generate testing data.
Abstract translation: 在特定实施例中，一种方法包括在耦合到半导体器件的控制器处接收测试激活信号。 该方法还包括响应于所接收的测试激活信号来偏置半导体器件的至少一个晶体管的阱。 该偏压由对控制器作出响应的偏置电路提供。 当井被偏置时，执行半导体器件的测试以产生测试数据。
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