公开(公告)号：US09553013B2

公开(公告)日：2017-01-24

申请号：US14633024

申请日：2015-02-26

Applicant: QUALCOMM Incorporated

Inventor： Michael A. Stuber ,  George Imthurn

IPC: H01L21/30 ,  H01L21/762 ,  H01L21/84 ,  H01L21/02 ,  H01L21/20 ,  H01L21/768 ,  H01L21/302 ,  H01L23/48 ,  H01L29/78 ,  H01L27/12 ,  B81C1/00

CPC classification number: H01L21/76251 ,  B81C1/00238 ,  B81C1/00698 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/02178 ,  H01L21/2007 ,  H01L21/302 ,  H01L21/76224 ,  H01L21/76256 ,  H01L21/76898 ,  H01L21/84 ,  H01L23/481 ,  H01L27/1203 ,  H01L29/7803 ,  H01L2224/80001 ,  H01L2224/9202 ,  H01L2924/1461 ,  H01L2924/00

Abstract: A method is disclosed. The method comprises fabricating a device layer on a top portion of a semiconductor wafer that comprises a substrate. The device layer comprises an active device. The method also comprises forming a trap rich layer at a top portion of a handle wafer. The forming comprises etching the top portion of the handle wafer to form a structure in the top portion of the handle wafer that configures the trap rich layer. The method also comprises bonding a top surface of the handle wafer to a top surface of the semiconductor wafer. The method also comprises removing a bottom substrate portion of the semiconductor wafer.

Abstract translation: 公开了一种方法。 该方法包括在包括衬底的半导体晶片的顶部上制造器件层。 器件层包括有源器件。 该方法还包括在处理晶片的顶部形成富含阱的层。 成形包括蚀刻处理晶片的顶部部分，以在构造陷阱富集层的手柄晶片的顶部部分中形成结构。 该方法还包括将手柄晶片的顶表面接合到半导体晶片的顶表面。 该方法还包括去除半导体晶片的底部衬底部分。

公开(公告)号：US10418465B1

公开(公告)日：2019-09-17

申请号：US15969986

申请日：2018-05-03

Applicant: QUALCOMM Incorporated

Inventor： Qingqing Liang ,  Francesco Carobolante ,  Sinan Goktepeli ,  George Imthurn ,  Fabio Alessio Marino ,  Narasimhulu Kanike

IPC: H01L29/792 ,  H01L29/66 ,  H01L29/788 ,  H01L27/11556 ,  G11C16/34 ,  G11C16/04 ,  H01L27/105 ,  H01L27/11 ,  H01L29/78

Abstract: Certain aspects of the present disclosure provide a memory device. One example memory device generally includes a first semiconductor region having a first region, a second region, and a third region, the second region being between the first region and the third region and having a different doping type than the first region and the third region. In certain aspects, the memory device also includes a first non-insulative region, a first insulative region being disposed between the first non-insulative region and the first semiconductor region. In certain aspects, the memory device may include a second non-insulative region, and a second insulative region disposed between the second region and the second non-insulative region, wherein the first insulative region and the second insulative region are disposed adjacent to opposite sides of the second region.