公开(公告)号：US20160072492A1

公开(公告)日：2016-03-10

申请号：US14477367

申请日：2014-09-04

Applicant: QUALCOMM Incorporated

Inventor： Lior Amarilio ,  Alexander Golubitski ,  Haim Hagay Haller ,  Felix Kolmakov ,  Gilad Sthoeger

IPC: H03K5/13 ,  G06F13/40 ,  G06F13/42 ,  G11C19/00

CPC classification number: H03K5/133 ,  G06F1/10 ,  G06F13/4068 ,  G06F13/4221 ,  G11C19/00 ,  H03K5/13 ,  H03K2005/0015 ,  Y02D10/14 ,  Y02D10/151

Abstract: Delay circuits, and related systems and methods are disclosed. In one aspect, a delay circuit is provided that uses logic to delay accurately an output enable signal to reduce or avoid data hazards within a slave device. The delay circuit includes two shift register chains configured to receive an output enable in signal based on a slow clock. A first shift register chain is clocked by a positive edge of a fast clock, and provides a first strobe signal. A second shift register chain is clocked by a negative edge of the fast clock, and provides a second strobe signal. The logic uses the first and second strobe signals, and the output enable in signal, to provide a delayed output enable out signal. The delay circuit provides a highly accurate time delay for the output enable signal to reduce or avoid data hazards in an area and power efficient manner.

Abstract translation: 公开了延迟电路及相关的系统和方法。 在一个方面，提供延迟电路，其使用逻辑来精确地延迟输出使能信号，以减少或避免从设备内的数据危害。 延迟电路包括两个移位寄存器链，其被配置为基于慢时钟接收信号中的输出使能。 第一移位寄存器链由快速时钟的上升沿提供时钟，并提供第一个选通信号。 第二移位寄存器链由快速时钟的负沿计时，并提供第二选通信号。 该逻辑使用第一和第二选通信号，以及信号中的输出使能，以提供延迟的输出使能输出信号。 延迟电路为输出使能信号提供高度准确的时间延迟，以减少或避免一个区域的数据危害和功率有效的方式。

公开(公告)号：US20190258486A1

公开(公告)日：2019-08-22

申请号：US16281290

申请日：2019-02-21

Applicant: QUALCOMM Incorporated

Inventor： Oren Nishry ,  Tomer Rafael Ben-Chen ,  Sharon Graif ,  Felix Kolmakov

IPC: G06F9/30 ,  G06F9/35

Abstract: Event-based branching for serial protocol processor-based devices is disclosed. In this regard, a serial protocol processor-based device provides an event mesh control circuit comprising a mapping table circuit and a register control array corresponding to rows of the mapping table circuit. Each row of the mapping table circuit of the event mesh control circuit represents an implementation-specific grouping of events, with each column of the row representing a last known status or outcome for a corresponding event. A microcontroller of the serial protocol processor-based device is configured to use the register control array to select which event (i.e., which column of a corresponding row) will be used to make a branching determination. A branch custom instruction provided by the microcontroller indicates a selected row, a branch target address, and a comparison value to compare against the event indicated by the register control array entry corresponding to the selected row.

公开(公告)号：US09520865B2

公开(公告)日：2016-12-13

申请号：US14477367

申请日：2014-09-04

Applicant: QUALCOMM Incorporated

Inventor： Lior Amarilio ,  Alexander Golubitski ,  Haim Hagay Haller ,  Felix Kolmakov ,  Gilad Sthoeger

IPC: G06F1/12 ,  H03K5/13 ,  G11C19/00 ,  G06F13/40 ,  G06F13/42 ,  G06F1/10 ,  H03K5/00

CPC classification number: H03K5/133 ,  G06F1/10 ,  G06F13/4068 ,  G06F13/4221 ,  G11C19/00 ,  H03K5/13 ,  H03K2005/0015 ,  Y02D10/14 ,  Y02D10/151

Abstract: Delay circuits, and related systems and methods are disclosed. In one aspect, a delay circuit is provided that uses logic to delay accurately an output enable signal to reduce or avoid data hazards within a slave device. The delay circuit includes two shift register chains configured to receive an output enable in signal based on a slow clock. A first shift register chain is clocked by a positive edge of a fast clock, and provides a first strobe signal. A second shift register chain is clocked by a negative edge of the fast clock, and provides a second strobe signal. The logic uses the first and second strobe signals, and the output enable in signal, to provide a delayed output enable out signal. The delay circuit provides a highly accurate time delay for the output enable signal to reduce or avoid data hazards in an area and power efficient manner.

Abstract translation: 公开了延迟电路及相关的系统和方法。 在一个方面，提供延迟电路，其使用逻辑来精确地延迟输出使能信号，以减少或避免从设备内的数据危害。 延迟电路包括两个移位寄存器链，其被配置为基于慢时钟接收信号中的输出使能。 第一移位寄存器链由快速时钟的上升沿提供时钟，并提供第一个选通信号。 第二移位寄存器链由快速时钟的负沿计时，并提供第二选通信号。 该逻辑使用第一和第二选通信号，以及信号中的输出使能，以提供延迟的输出使能输出信号。 延迟电路为输出使能信号提供高度准确的时间延迟，以减少或避免一个区域的数据危害和功率有效的方式。