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    SUBTHRESHOLD METAL OXIDE SEMICONDUCTOR FOR LARGE RESISTANCE
    2.
    发明申请
    SUBTHRESHOLD METAL OXIDE SEMICONDUCTOR FOR LARGE RESISTANCE 审中-公开
    用于大电阻的硫化金属氧化物半导体

    公开(公告)号：US20160173072A1

    公开(公告)日：2016-06-16

    申请号：US14642309

    申请日：2015-03-09

    Applicant: QUALCOMM Incorporated

    Inventor： Mazhareddin TAGHIVAND ,  Yashar RAJAVI ,  Alireza KHALILI

    IPC: H03K5/08

    CPC classification number: H03K5/08 ,  H03H1/02 ,  H03H11/245

    Abstract: Certain aspects of the present disclosure generally relate to generating a large electrical resistance. One example circuit generally includes a first transistor having a gate, a source connected with a first node of the circuit, and a drain connected with a second node of the circuit. The circuit may also include a voltage-limiting device connected between the gate and the source of the first transistor, wherein the device, if forward biased, is configured to limit a gate-to-source voltage of the first transistor such that the first transistor operates in a sub-threshold region. The circuit may further include a second transistor configured to bias the voltage-limiting device with a current, wherein a drain of the second transistor is connected with the gate of the first transistor, a gate of the second transistor is connected with the first node, and a source of the second transistor is connected with an electric potential.

    Abstract translation: 本公开的某些方面通常涉及产生大的电阻。 一个示例电路通常包括具有栅极的第一晶体管，与电路的第一节点连接的源极和与该电路的第二节点连接的漏极。 电路还可以包括连接在第一晶体管的栅极和源极之间的电压限制器件，其中如果正向偏置，器件被配置为限制第一晶体管的栅极 - 源极电压，使得第一晶体管 在子阈值区域中运行。 电路还可以包括第二晶体管，其被配置为用电流来偏压限流器件，其中第二晶体管的漏极与第一晶体管的栅极连接，第二晶体管的栅极与第一节点连接， 并且第二晶体管的源极与电势连接。

    APPARATUS AND METHOD FOR GENERATING QUADRUPLED REFERENCE CLOCK FROM SINGLE-ENDED CRYSTAL OSCILLATOR
    3.
    发明申请
    APPARATUS AND METHOD FOR GENERATING QUADRUPLED REFERENCE CLOCK FROM SINGLE-ENDED CRYSTAL OSCILLATOR 有权
    用于从单端晶体振荡器产生四参考时钟的装置和方法

    公开(公告)号：US20160164507A1

    公开(公告)日：2016-06-09

    申请号：US14640672

    申请日：2015-03-06

    Applicant: QUALCOMM Incorporated

    Inventor： Mohammad Bagher VAHID FAR ,  Alireza KHALILI ,  Yashar RAJAVI ,  Amirpouya KAVOUSIAN

    IPC: H03K5/00 ,  H03K3/013 ,  H03K3/012 ,  H03L7/00 ,  H03K3/017

    CPC classification number: H03K5/00006 ,  H03B19/10 ,  H03B19/14 ,  H03K5/1565

    Abstract: A method, an apparatus, and a computer program product are provided. The apparatus outputs a sinusoidal signal according to a first clock frequency, generates, a first digital signal having a 25% duty cycle based on the sinusoidal signal, generates a second digital signal having a 25% duty cycle based on the sinusoidal signal, combines the first digital signal and the second digital signal to generate a combined digital signal having a 50% duty cycle and a second clock frequency that is double the first clock frequency, and doubles the second clock frequency of the combined digital signal to generate an output signal having a third clock frequency that is quadruple the first clock frequency. The apparatus further generates a first control voltage and a second control voltage for the first buffer and a third control voltage for the second buffer based on the output signal.

    Abstract translation: 提供了一种方法，装置和计算机程序产品。 该装置根据第一时钟频率输出正弦信号，产生基于正弦信号的具有25％占空比的第一数字信号，产生基于正弦信号具有25％占空比的第二数字信号， 第一数字信号和第二数字信号，以产生具有50％占空比和第二时钟频率的组合数字信号，该第二时钟频率是第一时钟频率的两倍，并且使组合数字信号的第二时钟频率加倍，以产生具有 第三个时钟频率是第一个时钟频率的四倍。 该装置还基于输出信号产生用于第一缓冲器的第一控制电压和第二控制电压以及第二缓冲器的第三控制电压。

    LEAKAGE COMPENSATION CIRCUIT FOR PHASE-LOCKED LOOP (PLL) LARGE THIN OXIDE CAPACITORS
    4.
    发明申请
    LEAKAGE COMPENSATION CIRCUIT FOR PHASE-LOCKED LOOP (PLL) LARGE THIN OXIDE CAPACITORS 审中-公开
    用于相位锁定环路（PLL）的大型氧化物电容器的泄漏补偿电路

    公开(公告)号：US20160373116A1

    公开(公告)日：2016-12-22

    申请号：US15257578

    申请日：2016-09-06

    Applicant: QUALCOMM Incorporated

    Inventor： Mohammad Bagher VAHID FAR ,  Ara BICAKCI ,  Alireza KHALILI ,  Ashkan BORNA ,  Thinh Cat NGUYEN

    IPC: H03L7/08 ,  H03L7/089 ,  H03L7/093 ,  H02M3/07

    CPC classification number: H03L7/0802 ,  H02M3/07 ,  H03L7/0891 ,  H03L7/093

    Abstract: Certain aspects of the present disclosure provide methods and apparatus for compensating, or at least adjusting, for capacitor leakage. One example method generally includes determining a leakage voltage corresponding to a leakage current of a capacitor in a filter for a phase-locked loop (PLL), wherein the determining comprises closing a set of switches for discontinuous sampling of the leakage voltage; based on the sampled leakage voltage, generating a sourced current approximately equal to the leakage current; and injecting the sourced current into the capacitor.

    Abstract translation: 本公开的某些方面提供了用于补偿或至少调整电容器泄漏的方法和装置。 一个示例性方法通常包括确定对应于用于锁相环（PLL）的滤波器中的电容器的漏电流的泄漏电压，其中所述确定包括闭合一组开关以不连续地采样泄漏电压; 基于采样的泄漏电压，产生大致等于泄漏电流的源电流; 并将源电流注入电容器。

    APPARATUS AND METHOD FOR QUADRUPLING FREQUENCY OF REFERENCE CLOCK
    5.
    发明申请
    APPARATUS AND METHOD FOR QUADRUPLING FREQUENCY OF REFERENCE CLOCK 审中-公开
    用于对准时钟频率的装置和方法

    公开(公告)号：US20160099729A1

    公开(公告)日：2016-04-07

    申请号：US14605734

    申请日：2015-01-26

    Applicant: QUALCOMM Incorporated

    Inventor： Yashar RAJAVI ,  Alireza KHALILI ,  Amirpouya KAVOUSIAN ,  Mohammad Mahdi GHAHRAMANI ,  Mohammad Bagher VAHID FAR

    IPC: H04B1/04 ,  H04B15/04 ,  H04L7/00

    CPC classification number: H03K4/023 ,  H03B19/10 ,  H03F3/24 ,  H03K3/0315 ,  H04B2001/0408

    Abstract: A method, an apparatus, and a computer program product are provided. The apparatus outputs a first sinusoidal signal and a second sinusoidal signal according to a first clock frequency, generates, a first digital signal having a 25% duty cycle based on the first sinusoidal signal, generates a second digital signal having a 25% duty cycle based on the second sinusoidal signal, combines the first digital signal and the second digital signal to generate a combined digital signal having a 50% duty cycle and a second clock frequency that is double the first clock frequency, and doubles the second clock frequency of the combined digital signal to generate an output signal having a third clock frequency that is quadruple the first clock frequency. The apparatus further generates a control voltage for the first buffer and the second buffer based on the combined digital signal.

    Abstract translation: 提供了一种方法，装置和计算机程序产品。 该装置根据第一时钟频率输出第一正弦信号和第二正弦信号，产生基于第一正弦信号具有25％占空比的第一数字信号，产生基于25％占空比的第二数字信号 在第二正弦信号上，组合第一数字信号和第二数字信号以产生具有50％占空比和第二时钟频率的组合数字信号，该第二时钟频率是第一时钟频率的两倍，并且将组合的第二时钟频率加倍 数字信号以产生具有第三时钟频率的输出信号，该第三时钟频率是第一时钟频率的四倍。 该装置还基于组合的数字信号产生用于第一缓冲器和第二缓冲器的控制电压。

    INCREASED SYNTHESIZER PERFORMANCE IN CARRIER AGGREGATION/MULTIPLE-INPUT, MULTIPLE-OUTPUT SYSTEMS
    6.
    发明申请
    INCREASED SYNTHESIZER PERFORMANCE IN CARRIER AGGREGATION/MULTIPLE-INPUT, MULTIPLE-OUTPUT SYSTEMS 有权
    运输车辆集成/多输入多输出系统中增强的合成器性能

    公开(公告)号：US20160072512A1

    公开(公告)日：2016-03-10

    申请号：US14548705

    申请日：2014-11-20

    Applicant: QUALCOMM Incorporated

    Inventor： Alireza KHALILI ,  Mazhareddin TAGHIVAND ,  Arvind KEERTI

    IPC: H03L7/099 ,  H03B5/12

    CPC classification number: H03L7/099 ,  H03B5/1212 ,  H04B1/005 ,  H04B1/0064

    Abstract: Certain aspects of the present disclosure provide methods and apparatus for using multiple voltage-controlled oscillators (VCOs) to increase frequency synthesizer performance, such as in stringent multiple-input, multiple-output (MIMO) modes. One example apparatus capable of generating oscillating signals generally includes a first VCO, a second VCO, and connection circuitry configured to connect the second VCO in parallel with the first VCO if a phase-locked loop (PLL) associated with the second VCO is idle.

    Abstract translation: 本公开的某些方面提供了使用多个压控振荡器（VCO）来增加频率合成器性能的方法和装置，例如在严格的多输入多输出（MIMO）模式中。 能够产生振荡信号的一个示例性装置通常包括第一VCO，第二VCO和连接电路，其被配置为如果与第二VCO相关联的锁相环（PLL）空闲，则将第二VCO与第一VCO并联连接。

    DISTRIBUTED ACTIVE POWER COMBINING AMPLIFIER
    7.
    发明申请
    DISTRIBUTED ACTIVE POWER COMBINING AMPLIFIER 有权

    公开(公告)号：US20220109405A1

    公开(公告)日：2022-04-07

    申请号：US17490683

    申请日：2021-09-30

    Applicant: QUALCOMM INCORPORATED

    Inventor： Alireza KHALILI ,  Amir ZIABASHARHAGH ,  Beomsup KIM

    IPC: H03F1/02 ,  H03F3/24 ,  H03F1/56 ,  H03F3/195

    Abstract: A distributed active, power combining amplifier including at least one main amplifier having a first main portion and a second main portion, at least one peaking amplifier having a first peaking portion and a second peaking portion, and a transformer having a primary side and a secondary side, the primary side having at least a first primary segment, a second primary segment, a third primary segment and a fourth primary segment, wherein the first main portion is coupled to the first primary segment and the second primary segment, the first peaking portion is coupled to the first primary segment or the second primary segment, the second main portion is coupled to the third primary segment and the fourth primary segment, and the second peaking portion is coupled to the third primary segment or the fourth primary segment in a symmetric architecture.

    OVERLAPPING UNCOUPLED INDUCTORS FOR LOW-COST MULTI-FREQUENCY VOLTAGE-CONTROLLED OSCILLATORS
    9.
    发明申请
    OVERLAPPING UNCOUPLED INDUCTORS FOR LOW-COST MULTI-FREQUENCY VOLTAGE-CONTROLLED OSCILLATORS 有权
    用于低成本多电压控制振荡器的超重电感

    公开(公告)号：US20170019066A1

    公开(公告)日：2017-01-19

    申请号：US14801535

    申请日：2015-07-16

    Applicant: QUALCOMM Incorporated

    Inventor： Mohammad FARAZIAN ,  Amirpouya KAVOUSIAN ,  Alireza KHALILI

    IPC: H03B5/12

    CPC classification number: H03B5/1256 ,  H03B5/08 ,  H03B5/12 ,  H03B5/1206

    Abstract: Certain aspects of the present disclosure provide techniques and apparatus for generating multiple oscillating signals. One example circuit generally includes a first voltage-controlled oscillator (VCO) having a first inductor and a second VCO having a second inductor in parallel with a third inductor, wherein the second and third inductors are disposed inside a loop of the first inductor and may behave as a magnetic dipole. The loop of the first inductor may be symmetrical, and a combined geometry of loops of the second and third inductors may be symmetrical. The coupling coefficient (k) between the first inductor and a combination of the second and third inductors may be small (e.g., k

    Abstract translation: 本公开的某些方面提供了用于产生多个振荡信号的技术和装置。 一个示例电路通常包括具有第一电感器的第一压控振荡器（VCO）和具有与第三电感器并联的第二电感器的第二VCO，其中第二和第三电感器设置在第一电感器的环路内，并且可以 表现为磁偶极子。 第一电感器的环路可以是对称的，并且第二和第三电感器的环路的组合几何形状可以是对称的。 由于电路布局的对称几何形状，第一电感器和第二和第三电感器的组合之间的耦合系数（k）可能很小（例如，k <0.01）。 利用较小的k，第一和第二VCO的电感器可以彼此更靠近地放置，从而减少两个VCO消耗的面积。

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