公开(公告)号：US20160241380A1

公开(公告)日：2016-08-18

申请号：US14625518

申请日：2015-02-18

Applicant: QUALCOMM Incorporated

Inventor： Mohammad Mahdi GHAHRAMANI ,  Mazhareddin TAGHIVAND ,  Niranjan Anand TALWALKAR

IPC: H04L7/00 ,  H04L7/033 ,  H04B5/00

CPC classification number: H04L7/0012 ,  H04B5/0031 ,  H04L7/0331

Abstract: An example method for active load modulation includes determining a modulated portion and an unmodulated portion of a bit. Further, the example method includes during the modulated portion of the bit, holding a phase of a received carrier signal. In addition, the example method includes, during the unmodulated portion of the bit, synchronizing to the received carrier signal.

Abstract translation: 用于有源负载调制的示例性方法包括确定位的调制部分和未调制部分。 此外，示例性方法包括在比特的调制部分期间保持所接收的载波信号的相位。 此外，示例方法包括在位的未调制部分期间与接收到的载波信号同步。

公开(公告)号：US20160065179A1

公开(公告)日：2016-03-03

申请号：US14471608

申请日：2014-08-28

Applicant: QUALCOMM Incorporated

Inventor： Mazhareddin TAGHIVAND ,  Tong ZHANG ,  Mohammad Mahdi GHAHRAMANI

IPC: H03H11/12 ,  H03H11/22

CPC classification number: H03H11/1204 ,  H03H7/0153 ,  H03H7/21 ,  H03H11/22 ,  H03H17/0273 ,  H03H2218/04

Abstract: Certain aspects of the present disclosure provide circuits for generating high accuracy millimeter wave or radio frequency (RF) wideband in-phase (I) and quadrature (Q) oscillating signals having acceptable amplitude and phase mismatch over process, voltage, and temperature (PVT) variations with reduced cost, area, and power consumption. In one example apparatus, a polyphase filter having a first stage and a second stage is provided. Each stage comprises resistive elements and capacitive elements. Certain aspects of the present disclosure provide for intentional resistive and/or capacitive value mismatch between the resistive or capacitive values of one or multiple stages such that the phase mismatch between the resulting I and Q signals may be reduced without degrading the amplitude mismatch. Certain aspects of the present disclosure provide for replacing the resistive elements in at least one stage with transistors operating in the triode region, where the on-resistance is controlled by a feedback network.

Abstract translation: 本公开的某些方面提供用于产生在过程，电压和温度（PVT）上具有可接受的幅度和相位失配的高精度毫米波或射频（RF）宽带同相（I）和正交（Q）振荡信号的电路， 降低成本，面积和功耗的变化。 在一个示例性装置中，提供具有第一阶段和第二阶段的多相滤波器。 每个级包括电阻元件和电容元件。 本公开的某些方面提供一个或多个级的电阻或电容值之间的有意的电阻和/或电容值失配，使得可以在不降低幅度失配的情况下减小所产生的I和Q信号之间的相位失配。 本公开的某些方面提供了在三极管区域中操作的晶体管在至少一个级中替换电阻元件，其中导通电阻由反馈网络控制。

公开(公告)号：US20160099729A1

公开(公告)日：2016-04-07

申请号：US14605734

申请日：2015-01-26

Applicant: QUALCOMM Incorporated

Inventor： Yashar RAJAVI ,  Alireza KHALILI ,  Amirpouya KAVOUSIAN ,  Mohammad Mahdi GHAHRAMANI ,  Mohammad Bagher VAHID FAR

IPC: H04B1/04 ,  H04B15/04 ,  H04L7/00

CPC classification number: H03K4/023 ,  H03B19/10 ,  H03F3/24 ,  H03K3/0315 ,  H04B2001/0408

Abstract: A method, an apparatus, and a computer program product are provided. The apparatus outputs a first sinusoidal signal and a second sinusoidal signal according to a first clock frequency, generates, a first digital signal having a 25% duty cycle based on the first sinusoidal signal, generates a second digital signal having a 25% duty cycle based on the second sinusoidal signal, combines the first digital signal and the second digital signal to generate a combined digital signal having a 50% duty cycle and a second clock frequency that is double the first clock frequency, and doubles the second clock frequency of the combined digital signal to generate an output signal having a third clock frequency that is quadruple the first clock frequency. The apparatus further generates a control voltage for the first buffer and the second buffer based on the combined digital signal.

Abstract translation: 提供了一种方法，装置和计算机程序产品。 该装置根据第一时钟频率输出第一正弦信号和第二正弦信号，产生基于第一正弦信号具有25％占空比的第一数字信号，产生基于25％占空比的第二数字信号 在第二正弦信号上，组合第一数字信号和第二数字信号以产生具有50％占空比和第二时钟频率的组合数字信号，该第二时钟频率是第一时钟频率的两倍，并且将组合的第二时钟频率加倍 数字信号以产生具有第三时钟频率的输出信号，该第三时钟频率是第一时钟频率的四倍。 该装置还基于组合的数字信号产生用于第一缓冲器和第二缓冲器的控制电压。