公开(公告)号：US20160099729A1

公开(公告)日：2016-04-07

申请号：US14605734

申请日：2015-01-26

Applicant: QUALCOMM Incorporated

Inventor： Yashar RAJAVI ,  Alireza KHALILI ,  Amirpouya KAVOUSIAN ,  Mohammad Mahdi GHAHRAMANI ,  Mohammad Bagher VAHID FAR

IPC: H04B1/04 ,  H04B15/04 ,  H04L7/00

CPC classification number: H03K4/023 ,  H03B19/10 ,  H03F3/24 ,  H03K3/0315 ,  H04B2001/0408

Abstract: A method, an apparatus, and a computer program product are provided. The apparatus outputs a first sinusoidal signal and a second sinusoidal signal according to a first clock frequency, generates, a first digital signal having a 25% duty cycle based on the first sinusoidal signal, generates a second digital signal having a 25% duty cycle based on the second sinusoidal signal, combines the first digital signal and the second digital signal to generate a combined digital signal having a 50% duty cycle and a second clock frequency that is double the first clock frequency, and doubles the second clock frequency of the combined digital signal to generate an output signal having a third clock frequency that is quadruple the first clock frequency. The apparatus further generates a control voltage for the first buffer and the second buffer based on the combined digital signal.

Abstract translation: 提供了一种方法，装置和计算机程序产品。 该装置根据第一时钟频率输出第一正弦信号和第二正弦信号，产生基于第一正弦信号具有25％占空比的第一数字信号，产生基于25％占空比的第二数字信号 在第二正弦信号上，组合第一数字信号和第二数字信号以产生具有50％占空比和第二时钟频率的组合数字信号，该第二时钟频率是第一时钟频率的两倍，并且将组合的第二时钟频率加倍 数字信号以产生具有第三时钟频率的输出信号，该第三时钟频率是第一时钟频率的四倍。 该装置还基于组合的数字信号产生用于第一缓冲器和第二缓冲器的控制电压。

公开(公告)号：US20180076765A1

公开(公告)日：2018-03-15

申请号：US15638183

申请日：2017-06-29

Applicant: QUALCOMM Incorporated

Inventor： Mazhareddin TAGHIVAND ,  Alireza KHALILI ,  Mohammad EMADI ,  Yashar RAJAVI

IPC: H03B1/04 ,  H03B5/12

CPC classification number: H03B1/04 ,  H03B5/1212 ,  H03B5/1228 ,  H03B5/124 ,  H03B27/00 ,  H03B2200/0054 ,  H03B2200/007 ,  H03B2200/009

Abstract: Certain aspects of the present disclosure provide methods and apparatus for reducing phase noise in voltage-controlled oscillators (VCOs). One example VCO generally includes a first resonant circuit comprising an inductor and a first variable capacitive element coupled in parallel with the inductor; and a second variable capacitive element coupled to a center tap of the inductor and further coupled to a reference voltage, wherein the center tap of the inductor is further coupled to a voltage source.

公开(公告)号：US20170244415A1

公开(公告)日：2017-08-24

申请号：US15051156

申请日：2016-02-23

Applicant: QUALCOMM Incorporated

Inventor： Yashar RAJAVI ,  Jeongsik YANG ,  Emilia Vailun LEI

IPC: H03K21/02 ,  H03K3/037 ,  H03K3/3562

CPC classification number: H03K21/026 ,  H03K3/0372 ,  H03K3/3562 ,  H03L7/08

Abstract: The present disclosure describes current steering phase control for current-mode logic (CML) circuits. In some aspects, a circuit for frequency division comprises a current sink connected to a ground rail. The circuit also includes first and second current-carrying branches of frequency-dividing circuitry operably connected to respective load resistors, which are connected to a power rail. A first switch element of the circuit is connected between the current sink and the first current-carrying branch and a second switch element of the circuit is connected between the current sink and the second current-carrying branch. The first and second switch elements may steer current sank by the current sink between the first and second current-carrying branches effective to alter a phase of a signal provided by the frequency division circuit.

公开(公告)号：US20160173072A1

公开(公告)日：2016-06-16

申请号：US14642309

申请日：2015-03-09

Applicant: QUALCOMM Incorporated

Inventor： Mazhareddin TAGHIVAND ,  Yashar RAJAVI ,  Alireza KHALILI

IPC: H03K5/08

CPC classification number: H03K5/08 ,  H03H1/02 ,  H03H11/245

Abstract: Certain aspects of the present disclosure generally relate to generating a large electrical resistance. One example circuit generally includes a first transistor having a gate, a source connected with a first node of the circuit, and a drain connected with a second node of the circuit. The circuit may also include a voltage-limiting device connected between the gate and the source of the first transistor, wherein the device, if forward biased, is configured to limit a gate-to-source voltage of the first transistor such that the first transistor operates in a sub-threshold region. The circuit may further include a second transistor configured to bias the voltage-limiting device with a current, wherein a drain of the second transistor is connected with the gate of the first transistor, a gate of the second transistor is connected with the first node, and a source of the second transistor is connected with an electric potential.

Abstract translation: 本公开的某些方面通常涉及产生大的电阻。 一个示例电路通常包括具有栅极的第一晶体管，与电路的第一节点连接的源极和与该电路的第二节点连接的漏极。 电路还可以包括连接在第一晶体管的栅极和源极之间的电压限制器件，其中如果正向偏置，器件被配置为限制第一晶体管的栅极 - 源极电压，使得第一晶体管 在子阈值区域中运行。 电路还可以包括第二晶体管，其被配置为用电流来偏压限流器件，其中第二晶体管的漏极与第一晶体管的栅极连接，第二晶体管的栅极与第一节点连接， 并且第二晶体管的源极与电势连接。

公开(公告)号：US20160164507A1

公开(公告)日：2016-06-09

申请号：US14640672

申请日：2015-03-06

Applicant: QUALCOMM Incorporated

Inventor： Mohammad Bagher VAHID FAR ,  Alireza KHALILI ,  Yashar RAJAVI ,  Amirpouya KAVOUSIAN

IPC: H03K5/00 ,  H03K3/013 ,  H03K3/012 ,  H03L7/00 ,  H03K3/017

CPC classification number: H03K5/00006 ,  H03B19/10 ,  H03B19/14 ,  H03K5/1565

Abstract: A method, an apparatus, and a computer program product are provided. The apparatus outputs a sinusoidal signal according to a first clock frequency, generates, a first digital signal having a 25% duty cycle based on the sinusoidal signal, generates a second digital signal having a 25% duty cycle based on the sinusoidal signal, combines the first digital signal and the second digital signal to generate a combined digital signal having a 50% duty cycle and a second clock frequency that is double the first clock frequency, and doubles the second clock frequency of the combined digital signal to generate an output signal having a third clock frequency that is quadruple the first clock frequency. The apparatus further generates a first control voltage and a second control voltage for the first buffer and a third control voltage for the second buffer based on the output signal.

Abstract translation: 提供了一种方法，装置和计算机程序产品。 该装置根据第一时钟频率输出正弦信号，产生基于正弦信号的具有25％占空比的第一数字信号，产生基于正弦信号具有25％占空比的第二数字信号， 第一数字信号和第二数字信号，以产生具有50％占空比和第二时钟频率的组合数字信号，该第二时钟频率是第一时钟频率的两倍，并且使组合数字信号的第二时钟频率加倍，以产生具有 第三个时钟频率是第一个时钟频率的四倍。 该装置还基于输出信号产生用于第一缓冲器的第一控制电压和第二控制电压以及第二缓冲器的第三控制电压。