公开(公告)号：US11001143B2

公开(公告)日：2021-05-11

申请号：US16225481

申请日：2018-12-19

Applicant: QUALCOMM Incorporated

Inventor： Rahul Gulati ,  John Chi Kit Wong ,  Peter Koster ,  Reza Kakoee ,  Thomas Dannemann

IPC: B60K35/00 ,  G06F3/14 ,  H03M13/09

Abstract: Systems, methods, and devices of the various embodiments enable dynamic configuration of a number of display regions of interest (ROIs) associated with safety critical content presented on a display, such as a vehicle display. Various embodiments may enable verification of data integrity for ROIs on a display. Various embodiments may enable the selection of different sets of display ROIs from a plurality of independent sets of display ROIs each associated with its own set of stored integrity check values (ICVs). Various embodiments may enable stored ICVs to be used to verify the data integrity of ROIs on a display. Various embodiments may enable the set of display ROIs and the associated ICVs for each display ROI to be changed after a number of frames have been displayed.

公开(公告)号：US20190018408A1

公开(公告)日：2019-01-17

申请号：US15648347

申请日：2017-07-12

Applicant: QUALCOMM Incorporated

Inventor： Rahul Gulati ,  Mainak Biswas ,  Pranjal Bhuyan ,  Anshuman Saxena

IPC: G05D1/00 ,  G05D1/02 ,  G08G1/0962 ,  G08G1/0968 ,  G07C5/00

Abstract: Devices and methods are disclosed for verifying the integrity of a sensing system. In one aspect, a vehicle includes an integrated circuit configured to support a message-based protocol between the integrated circuit and a sensor device associated with the vehicle, and send a sensor capability safety support message, as part of the message-based protocol, to determine one or more capabilities of the sensor device. The integrated circuit is also configured to receive, in response to the sensor capability safety support message, identification data corresponding to the sensor device, from the sensor device. The memory is configured to store a plurality of request data corresponding to a plurality of fields supported by the message-based protocol and associated with the integrated circuit and the sensor device capabilities, and store the response, including the identification data, from the sensor device.

公开(公告)号：US10134139B2

公开(公告)日：2018-11-20

申请号：US15458488

申请日：2017-03-14

Applicant: QUALCOMM Incorporated

Inventor： Rahul Gulati ,  Alex Kwang Ho Jong ,  John Chi Kit Wong ,  Sanjay Gupta ,  Ike Ikizyan

IPC: G06K9/00 ,  G06T7/11

Abstract: Techniques of this disclosure may include processing one or more regions-of-interest (ROI) of an input image through a model of a display processor, calculating a first data integrity check value on the one or more ROI of the input image after processing through the model, processing the input image by the display processor, calculating a second data integrity check value on the one or more ROI by the display processor after the display processor processes the input image, comparing the first data integrity check value to the second data integrity check value, and generating an interrupt if the comparison indicates that the first data integrity check value and the second data integrity check value do not match.

公开(公告)号：US09955150B2

公开(公告)日：2018-04-24

申请号：US14864348

申请日：2015-09-24

Applicant: QUALCOMM Incorporated

Inventor： Rahul Gulati ,  John Chi Kit Wong ,  Pranjal Bhuyan ,  Sanjay Gupta ,  Hemang Jayant Shah

IPC: H04N17/00 ,  B60K35/00 ,  G09G3/00

CPC classification number: H04N17/004 ,  B60K35/00 ,  G09G3/006

Abstract: A display processor of a display system may receive an image that includes a test pattern. An input checksum may be associated with the test pattern. Hardware units of the display processor may process the image. The display system may generate an output checksum based at least in part on the test pattern after processing of the image. The display system may detect a fault in the hardware units of the display processor based on determining a difference between the input checksum and the output checksum.

公开(公告)号：US20170123897A1

公开(公告)日：2017-05-04

申请号：US14994078

申请日：2016-01-12

Applicant: QUALCOMM INCORPORATED

Inventor： Nhon Quach ,  Mainak Biswas ,  Pranjal Bhuyan ,  Jeffrey Shabel ,  Robert Hardacker ,  Rahul Gulati ,  Mattheus Heddes

IPC: G06F11/10 ,  G06F12/08

CPC classification number: G06F11/1064 ,  G06F11/1012 ,  G06F12/08 ,  G06F12/0888 ,  G06F2212/1032 ,  G06F2212/1044 ,  G06F2212/1056 ,  G06F2212/281 ,  G06F2212/401 ,  G06F2212/466

Abstract: Systems and methods are disclosed for error correction control (ECC) for a memory device comprising a data portion and an ECC portion, the memory device coupled to a system on a chip (SoC). The SoC includes an ECC cache. On receipt of a request to write a line of data to the memory, a determination is made if the data is compressible. If so, the data line is compressed. ECC bits are generated for the compressed or uncompressed data line. A determination is made if an ECC cache line is associated with the received data line. If the data line is compressible, the ECC bits are appended to the compressed data line and the appended data line is stored in the data portion of the memory. Otherwise, the ECC bits are stored in the ECC cache and the data line is stored in the data portion of the memory.

公开(公告)号：US11634895B2

公开(公告)日：2023-04-25

申请号：US17161731

申请日：2021-01-29

Applicant: QUALCOMM Incorporated

Inventor： Kiran Kumar Malipeddi ,  Rahul Gulati

IPC: E03C1/046

Abstract: Various embodiments include components (e.g., a processor in a vehicle advanced driver assistance system) configured to identify subsystems that require testing in order to verify their compliance with a safety requirement. The components may determine whether verification of compliance requires that the subsystems be tested at PON, at POFF, during runtime or a combination thereof, dynamically determine the achievable parallelism for testing the identified subsystems, dynamically determine coverage level requirements for performing or executing built in self tests (BISTs) on each identified subsystem, and perform or execute the BISTs on the subsystems at the determined level of parallel and at the determined coverage level.

公开(公告)号：US10901020B2

公开(公告)日：2021-01-26

申请号：US16118280

申请日：2018-08-30

Applicant: QUALCOMM Incorporated

Inventor： Palkesh Jain ,  Rahul Gulati ,  Edward Jacob Meisarosh

IPC: G01R29/027 ,  G06F1/10 ,  H03K3/037 ,  H03K7/08

Abstract: In one embodiment, a system including a duty-cycle-monitoring circuit is configured to receive a monitored signal having cycles that have a high portion and a low portion. The duty-cycle-monitoring circuit includes: a cascade of buffers including a first buffer, wherein the first buffer is configured to receive a first signal based on the monitored signal, a plurality of corresponding flip-flops. Each flip-flop is triggered by a second signal based on the monitored signal. The data input of each flip-flop is connected to an output of a corresponding buffer. The duty-cycle-monitoring circuit further includes a control circuit configured to determine, based on a state of the plurality of flip-flops, a measure of the duration of the high portion of a cycle of the monitored signal and determine, based on a state of the plurality of flip-flops, a measure of duration of the low portion of a cycle of the monitored signal.

公开(公告)号：US10482289B2

公开(公告)日：2019-11-19

申请号：US15685795

申请日：2017-08-24

Applicant: QUALCOMM Incorporated

Inventor： David Barr ,  Dafna Shaool ,  Rahul Gulati ,  Pranjal Bhuyan

IPC: G06F21/00 ,  G06F21/70 ,  G06F21/50 ,  G06F21/62 ,  G06F9/50

Abstract: A computing device includes a hardware resource, a component to send a transaction signal including a target address of the hardware resource, a security data associated with an initiator of the transaction signal, and a safety data associated with the initiator, and an access control unit coupled to the component and the hardware resource, the access control unit to receive the transaction signal, determine whether security access is granted based on the transaction signal, determine whether safety access is granted based on the transaction signal, and allow access to the hardware resource based on both the security access and the safety access being granted.

公开(公告)号：US10331532B2

公开(公告)日：2019-06-25

申请号：US15410271

申请日：2017-01-19

Applicant: QUALCOMM Incorporated

Inventor： Kapil Bansal ,  Kailash Digari ,  Rahul Gulati

IPC: G06F11/27 ,  G06F11/273 ,  G06F11/22 ,  G06F11/16

Abstract: Aspects disclosed herein relate to periodic non-intrusive diagnosis of lockstep systems. An exemplary method includes comparing execution of a program on a first processing system of the plurality of processing systems and execution of the program on a second processing system of the plurality of processing systems using a first comparator circuit, comparing the execution of the program on the first processing system and the execution of the program on the second processing system using a second comparator circuit, and running a diagnosis program on the second comparator circuit while the comparing using the first comparator circuit is ongoing.

公开(公告)号：US20190041440A1

公开(公告)日：2019-02-07

申请号：US15667116

申请日：2017-08-02

Applicant: QUALCOMM Incorporated

Inventor： Bipin Duggal ,  Rahul Gulati ,  Sina Dena

IPC: G01R23/02 ,  G01R35/00

Abstract: In certain aspects of the disclosure, a frequency monitor includes a counter configured to receive a monitored clock signal, to count a number of periods of the monitored clock signal over a predetermined time duration, and to output a count value corresponding to the number of periods of the monitored clock signal. The frequency monitor also includes a comparator configured to receive the count value from the counter, to receive an expected count value, to compare the count value from the counter with the expected count value, and to output a pass status signal or a fail status signal based on the comparison.