公开(公告)号：US20180300208A1

公开(公告)日：2018-10-18

申请号：US15486164

申请日：2017-04-12

Applicant: QUALCOMM Incorporated

Inventor： Kalyan Kumar Oruganti ,  Kailash Digari ,  Sandeep Nellikatte Srivatsa

IPC: G06F11/16 ,  G06F1/26 ,  G06F1/28 ,  G06F3/06 ,  G06F11/20

CPC classification number: G06F11/1666 ,  G06F1/263 ,  G06F1/28 ,  G06F1/3243 ,  G06F1/3275 ,  G06F1/3287 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0647 ,  G06F3/0683 ,  G06F9/46 ,  G06F11/2094 ,  G06F12/0868 ,  G06F2201/85 ,  G06F2212/1041 ,  G06F2212/205 ,  G11C5/14 ,  G11C11/005 ,  G11C14/00 ,  G11C29/32 ,  Y02D10/14

Abstract: An integrated circuit is disclosed for data retention with data migration. In an example aspect, the integrated circuit includes a logic block, a memory block, and retention control circuitry coupled to the logic and memory blocks. The logic block includes multiple retention-relevant storage devices to store first data and second data. The multiple retention-relevant storage devices include a first group of retention-relevant storage devices to store the first data and a second group of retention-relevant storage devices to store the second data. The memory block maintains memory data in the memory block during a retention operational mode. The retention control circuitry causes the retention-relevant storage devices of the second group to be activated into multiple scan chains and also migrates the second data between the second group and the memory block using the multiple scan chains to accommodate transitions between the retention operational mode and a regular operational mode.

公开(公告)号：US10331532B2

公开(公告)日：2019-06-25

申请号：US15410271

申请日：2017-01-19

Applicant: QUALCOMM Incorporated

Inventor： Kapil Bansal ,  Kailash Digari ,  Rahul Gulati

IPC: G06F11/27 ,  G06F11/273 ,  G06F11/22 ,  G06F11/16

Abstract: Aspects disclosed herein relate to periodic non-intrusive diagnosis of lockstep systems. An exemplary method includes comparing execution of a program on a first processing system of the plurality of processing systems and execution of the program on a second processing system of the plurality of processing systems using a first comparator circuit, comparing the execution of the program on the first processing system and the execution of the program on the second processing system using a second comparator circuit, and running a diagnosis program on the second comparator circuit while the comparing using the first comparator circuit is ongoing.

公开(公告)号：US10162922B2

公开(公告)日：2018-12-25

申请号：US15460127

申请日：2017-03-15

Applicant: QUALCOMM Incorporated

Inventor： Kalyan Kumar Oruganti ,  Kailash Digari ,  Sandeep Nellikatte Srivatsa

IPC: G06F17/50 ,  H03K19/00

Abstract: A computer-implemented method for generating a circuit design is provided according to certain aspects. The method includes determining a gating efficiency of first gate-enable logic, determining a gating efficiency of second gate-enable logic, and determining one of the first gate-enable logic and the second gate-enable logic having a greater one of the determined gating efficiencies. The method also includes placing the determined one of the first gate-enable logic and the second gate-enable logic in clock gating logic of the circuit design, and placing another one of the first gate-enable logic and the second gate-enable in data gating logic of the circuit design.

公开(公告)号：US20180268088A1

公开(公告)日：2018-09-20

申请号：US15460127

申请日：2017-03-15

Applicant: QUALCOMM Incorporated

Inventor： Kalyan Kumar Oruganti ,  Kailash Digari ,  Sandeep Nellikatte Srivatsa

IPC: G06F17/50 ,  H03K19/00

CPC classification number: G06F17/505 ,  H03K19/0016

Abstract: A computer-implemented method for generating a circuit design is provided according to certain aspects. The method includes determining a gating efficiency of first gate-enable logic, determining a gating efficiency of second gate-enable logic, and determining one of the first gate-enable logic and the second gate-enable logic having a greater one of the determined gating efficiencies. The method also includes placing the determined one of the first gate-enable logic and the second gate-enable logic in clock gating logic of the circuit design, and placing another one of the first gate-enable logic and the second gate-enable in data gating logic of the circuit design.

公开(公告)号：US10430302B2

公开(公告)日：2019-10-01

申请号：US15486164

申请日：2017-04-12

Applicant: QUALCOMM Incorporated

Inventor： Kalyan Kumar Oruganti ,  Kailash Digari ,  Sandeep Nellikatte Srivatsa

IPC: G06F11/00 ,  G06F11/16 ,  G06F1/26 ,  G06F1/28 ,  G06F3/06 ,  G06F11/20 ,  G06F1/3234 ,  G11C11/00 ,  G11C14/00 ,  G11C29/32 ,  G06F1/3287 ,  G06F9/46 ,  G11C5/14 ,  G06F12/0868

Abstract: An integrated circuit is disclosed for data retention with data migration. In an example aspect, the integrated circuit includes a logic block, a memory block, and retention control circuitry coupled to the logic and memory blocks. The logic block includes multiple retention-relevant storage devices to store first data and second data. The multiple retention-relevant storage devices include a first group of retention-relevant storage devices to store the first data and a second group of retention-relevant storage devices to store the second data. The memory block maintains memory data in the memory block during a retention operational mode. The retention control circuitry causes the retention-relevant storage devices of the second group to be activated into multiple scan chains and also migrates the second data between the second group and the memory block using the multiple scan chains to accommodate transitions between the retention operational mode and a regular operational mode.