公开(公告)号：US20200058330A1

公开(公告)日：2020-02-20

申请号：US16103319

申请日：2018-08-14

Applicant: QUALCOMM INCORPORATED

Inventor： PAWAN CHHABRA ,  VENKATA DEVARASETTY ,  MAYANK GUPTA ,  MAHESHWAR THAKUR SINGH ,  HARSHIT TIWARI

IPC: G11C5/14 ,  G06F1/32 ,  G11C11/4074 ,  G11C11/4076 ,  G11C7/20

Abstract: Systems and methods are disclosed for providing micro-idle memory power management. One embodiment of a method comprises receiving and storing an exit latency vote from each of a plurality of memory subsystems on a system on chip electrically coupled to a system memory. In response to a micro-idle memory state in which each of the memory subsystems are idle, a minimum exit latency value from the plurality of exit latency votes is determined. One of a plurality of system memory modes is selected which has a micro-idle sleep time that meets the minimum exit latency value while minimizing system memory power consumption. The selected system memory mode is initiated.

公开(公告)号：US20210191795A1

公开(公告)日：2021-06-24

申请号：US16722861

申请日：2019-12-20

Applicant: QUALCOMM INCORPORATED

Inventor： RAKESH MISRA ,  ROHIT GUPTA ,  SHUBHAM MAHESHWARI ,  PAWAN CHHABRA

IPC: G06F11/07 ,  G06F9/4401 ,  G06F1/3203 ,  G06F15/78

Abstract: A warm mission-mode reset may be performed in a portable computing device. Assertion of a signal indicating an error condition may be detected. In response to detection of the signal indicating an error condition, a signal indicating a request to preserve memory contents may be provided to a DRAM subsystem. Then, in response to a signal acknowledging the DRAM subsystem is preserving the memory contents, a system reset signal may be asserted.

公开(公告)号：US20170269984A1

公开(公告)日：2017-09-21

申请号：US15075011

申请日：2016-03-18

Applicant: QUALCOMM INCORPORATED

Inventor： ANANTHA IDAPALAPATI ,  AJAYKUMAR SHANKARGOUDA PATIL ,  SUBODH SINGH ,  RAMSWAROOP SOMANI ,  GOPI KRISHNA NEDANURI ,  PAWAN CHHABRA ,  SARBARTHA BANERJEE ,  VICTOR WONG

IPC: G06F11/07 ,  G06F13/24 ,  G06F11/14 ,  G06F13/28

CPC classification number: G06F11/0757 ,  G06F11/0721 ,  G06F11/1441 ,  G06F13/24 ,  G06F13/28

Abstract: Systems and methods are disclosed for improved processor hang detection. An exemplary method comprises setting a timer with a hang threshold value for each of a plurality of processors of a system on a chip (SoC). The hang threshold value represents a time in microseconds. The method further comprising receiving a first heartbeat signal from each of the plurality of processors with detection logic hardware of a hang controller coupled to the plurality of processors and to the timer. The timer is reset for each of the plurality of processors if a second heartbeat signal is received from the corresponding one of the plurality of processors before the timer expires. Alternatively, a hang event notification is generated if the second heartbeat signal is not received from the corresponding one of the plurality of processors before the timer expires.

公开(公告)号：US20150161057A1

公开(公告)日：2015-06-11

申请号：US14147555

申请日：2014-01-05

Applicant: Qualcomm Incorporated

Inventor： THOMAS M. ZENG ,  AZZEDINE TOUZNI ,  STEPHEN A. MOLLOY ,  SATYAKI MUKHERJEE ,  ABHIRAMI SENTHILKUMARAN ,  OLAV HAUGAN ,  TZUNG REN TZENG ,  TAREK ZGHAL ,  JEAN-LOUIS O. TARDIEUX ,  AJAY UPADHYAYA ,  ZHURANG ZHAO ,  PAWAN CHHABRA ,  SUBRAHMANYAM MOOLA ,  PAVAN KUMAR ,  JAYDEEP R. CHOKSHI ,  VICTOR K. WONG ,  VIPUL C. GANDHI

IPC: G06F12/10

CPC classification number: G06F12/1027 ,  G06F11/2221 ,  G11C29/18

Abstract: Systems and methods are disclosed for providing memory address translation for a memory management system. One embodiment of such a system comprises a memory device and an application processor in communication via a system interconnect. The application processor comprises test code for testing one or more of a plurality of hardware devices. Each of the hardware devices has a corresponding system memory management unit (SMMU) for processing memory requests associated with the hardware device to the memory device. The system further comprises a client-side address translation system in communication with the system interconnect and the plurality of SMMUs. The client-side address translation system is configured to selectively route stimulus traffic associated with the test code to a client port on one or more of the plurality of SMMUs for testing the corresponding hardware devices.

Abstract translation: 公开了用于为存储器管理系统提供存储器地址转换的系统和方法。 这种系统的一个实施例包括存储器设备和经由系统互连进行通信的应用处理器。 应用处理器包括用于测试多个硬件设备中的一个或多个的测试代码。 每个硬件设备具有相应的系统存储器管理单元（SMMU），用于处理与硬件设备相关联的存储器请求到存储器设备。 该系统还包括与系统互连和多个SMMU通信的客户端地址转换系统。 客户端地址转换系统被配置为选择性地将与测试代码相关联的刺激流量路由到多个SMMU中的一个或多个SMMU上的客户端口，以测试对应的硬件设备。