Abstract:
Systems and methods for external access detection and recovery in a subsystem of a system-on-a-chip (SoC) in a portable computing device (PCD) are presented. In operation, a subsystem of the SoC is operated independently of the rest of the SoC, such as when the SoC is in a non-functional or low power mode or state. The subsystem comprises a hardware agent in communication with a trace buffer. While the subsystem is operating independently of the rest of the SoC, the trace buffer captures trace data about the operation of the subsystem. During the operation of the subsystem, in response to identifying a trigger event, the trace buffer stops capturing the trace data, and a wake-up notification comprising a signal from the hardware agent to the SoC is communicated.
Abstract:
Communication channels among a connector port module, a debug interface module, and a power communication interface module may be established. Each of these elements may be part of a system-on-chip. The power communication interface module may be coupled to an integrated circuit, such as a power management integrated circuit. The connector port module may be coupled to a connector, in which the connector may facilitate connections between the PCD and one or more external devices, such as a testing/debugging device. The connector may comprise an SD connector. The connector may be monitored for a device present signal. If a device present signal has been detected, then it may be determined if a valid access code has been received for allowing access to communications within the PCD. If a valid access code is received, then a command may be issued to relinquish control of the integrated circuit from a master processor.
Abstract:
Systems and methods are disclosed for improved processor hang detection. An exemplary method comprises setting a timer with a hang threshold value for each of a plurality of processors of a system on a chip (SoC). The hang threshold value represents a time in microseconds. The method further comprising receiving a first heartbeat signal from each of the plurality of processors with detection logic hardware of a hang controller coupled to the plurality of processors and to the timer. The timer is reset for each of the plurality of processors if a second heartbeat signal is received from the corresponding one of the plurality of processors before the timer expires. Alternatively, a hang event notification is generated if the second heartbeat signal is not received from the corresponding one of the plurality of processors before the timer expires.
Abstract:
An integrated circuit includes a trace subsystem that provides timestamps for events occurring in a trace source that does not natively support time stamping trace data. A timestamp inserter is coupled to such a trace source. The timestamp inserter generates a modified trace data stream by arranging a reference or references with the trace information from the trace source on a trace bus. A trace destination receives the modified trace data stream including the reference(s). In some embodiments, a timestamp inserter receives a timestamp request and stores a reference in a buffer. Upon later receipt of trace information associated with the request, the timestamp inserter inserts the reference, a current reference and the received trace information into the trace data stream.
Abstract:
Systems, methods, and computer programs for managing trace data in a portable computing device are disclosed. One system includes a system-on-chip and a trace parser. The system-on-chip may have a plurality of trace sources for originating corresponding trace data and a trace system configured to receive and dump the trace data from one of the trace sources to a plurality of trace sinks. The trace parser is configured to reconstruct the trace data dumped to the plurality of trace sinks.