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    Methods And Apparatus For In-Memory Device Access Control
    1.
    发明申请
    Methods And Apparatus For In-Memory Device Access Control 有权

    公开(公告)号：US20220027520A1

    公开(公告)日：2022-01-27

    申请号：US16937907

    申请日：2020-07-24

    Applicant: QUALCOMM Incorporated

    Inventor： Yanru LI ,  Dexter Tamio CHUN

    IPC: G06F21/79 ,  G06F21/31 ,  G06F12/14 ,  G06F11/07

    Abstract: Various embodiments may include methods and systems for providing secure in-memory device access of a memory device by a system-on-a-chip (SOC). Various methods may include receiving a configuration message from the SOC for configuring a memory access control of the memory device, and configuring the memory access control based on the configuration message. Various embodiments may include receiving an access request message from the SOC requesting access to a memory base address and a memory access range of a memory cell array of the memory device, wherein the access request message includes a read/write operation. Various embodiments may include comparing the access request message with the configured memory access control to determine whether the access request message is allowable. Various embodiments may further include performing the read/write operation in response to determining that the access request message is allowable.

    PARTIAL REFRESH TECHNIQUE TO SAVE MEMORY REFRESH POWER
    2.
    发明申请
    PARTIAL REFRESH TECHNIQUE TO SAVE MEMORY REFRESH POWER 审中-公开

    公开(公告)号：US20200321051A1

    公开(公告)日：2020-10-08

    申请号：US16907103

    申请日：2020-06-19

    Applicant: QUALCOMM Incorporated

    Inventor： Jungwon SUH ,  Yanru LI ,  Michael Hawjing LO ,  Dexter Tamio CHUN

    IPC: G11C11/406 ,  G11C7/10

    Abstract: In a conventional memory subsystem, a memory controller issues explicit refresh commands to a DRAM memory device to maintain integrity of the data stored in the memory device when the memory device is in an auto-refresh mode. A significant amount of power may be consumed to carry out the refresh. To address this and other issues, it is proposed to allow a partial refresh in the auto-refresh mode in which the refreshing operation may be skipped for a subset of the memory cells. Through such selective refresh skipping, the power consumed for auto-refreshes may be reduced. Operating system kernels and memory drivers may be configured to determine areas of memory for which the refreshing operation can be skipped.

    MEMORY WITH SYSTEM ECC
    4.
    发明申请
    MEMORY WITH SYSTEM ECC 有权

    公开(公告)号：US20210064463A1

    公开(公告)日：2021-03-04

    申请号：US16944110

    申请日：2020-07-30

    Applicant: QUALCOMM Incorporated

    Inventor： Jungwon SUH ,  Michael Hawjing LO ,  Dexter Tamio CHUN ,  Xavier Loic LELOUP ,  Laurent Rene MOLL

    IPC: G06F11/10 ,  G06F3/06

    Abstract: Methods and apparatuses for a system error-correcting code function are presented. The apparatus includes a memory configured to communicate with a host. The memory includes a memory array configured to store data. The memory is configured to provide the data stored in the memory array to the host in performing computing functions and configured to provide an error-correction code (ECC) associated with the data to the host. The ECC is not stored in the memory array in a first configuration of the memory and is stored in the memory array in a second configuration of the memory.

    DYNAMIC LINK ERROR PROTECTION IN MEMORY SYSTEMS
    6.
    发明申请
    DYNAMIC LINK ERROR PROTECTION IN MEMORY SYSTEMS 审中-公开

    公开(公告)号：US20190324850A1

    公开(公告)日：2019-10-24

    申请号：US16503368

    申请日：2019-07-03

    Applicant: QUALCOMM Incorporated

    Inventor： Jungwon SUH ,  Alain ARTIERI ,  Dexter Tamio CHUN ,  Deepti Vijayalakshmi SRIRAMAGIRI

    IPC: G06F11/10 ,  G06F3/06

    Abstract: Errors can be introduced when data is transferred over a link between two entities such as between a host and a memory. Link error protection schemes can be implemented to detect and correct errors that occur on the link to enhance transmission reliability. However, these benefits are not without costs since such protection schemes increase both latency and power consumption. In one or more aspects, it is proposed to dynamically adjust the level of link error protection applied to match any change in the operating environment. For example, likelihood of link errors strongly correlates with the link speed. If the link speed is increased, a greater level of link error protection can be applied to counteract the increase in the link errors. If the link speed is decreased, the level of protection can be decreased so that latency and power consumption penalties can be minimized.

    TRANSACTION ELIMINATION USING METADATA
    8.
    发明申请
    TRANSACTION ELIMINATION USING METADATA 审中-公开

    公开(公告)号：US20180253258A1

    公开(公告)日：2018-09-06

    申请号：US15448203

    申请日：2017-03-02

    Applicant: QUALCOMM Incorporated

    Inventor： Jeffrey Hao CHU ,  Subrato Kumar DE ,  Dexter Tamio CHUN ,  Bohuslav RYCHLIK ,  Richard Alan STEWART

    IPC: G06F3/06 ,  G06F13/16

    CPC classification number: G06F3/0656 ,  G06F3/061 ,  G06F3/0625 ,  G06F3/0673 ,  G06F13/1668 ,  G06F13/1673 ,  G11C15/043

    Abstract: Various aspects are described herein. In some aspects, the present disclosure provides a method of communicating data between an electronic unit of a system-on-chip (SoC) and a dynamic random access memory (DRAM). The method includes initiating a memory transaction corresponding to first data. The method includes determining a non-unique first signature and a unique second signature associated with the first data based on content of the first data. The method includes determining if the non-unique first signature is stored in at least one of a local buffer on the SoC separate from the DRAM or the DRAM. The method includes determining if the unique second signature is stored in at least one of the local buffer or the DRAM based on determining the non-unique first signature is stored. The method includes eliminating the memory transaction with respect to the DRAM based on determining the unique second signature is stored.

    ACCESS CONTROL FOR PROTECTION OF IN-MEMORY COMPUTATION
    10.
    发明申请
    ACCESS CONTROL FOR PROTECTION OF IN-MEMORY COMPUTATION 有权

    公开(公告)号：US20220269439A1

    公开(公告)日：2022-08-25

    申请号：US17183903

    申请日：2021-02-24

    Applicant: QUALCOMM Incorporated

    Inventor： Dexter Tamio CHUN ,  Yanru LI

    IPC: G06F3/06 ,  G06F21/78

    Abstract: Protection of in memory or near memory computations may utilize a controller and an access path that is added through the control path to allow access control on the control path. In some examples, the memory compute request from the host may be intercepted and stopped. In addition, some examples the controller may synchronize the access control policy configuration on data path and control path, express the target address on the data bus instead of the address bus but instead is on the data bus, translate addresses using SWI groups, and the address may be filtered or blocked via the access controller.

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