公开(公告)号：US10892250B2

公开(公告)日：2021-01-12

申请号：US16229562

申请日：2018-12-21

Applicant: Powertech Technology Inc.

Inventor： Ming-Chih Chen ,  Hung-Hsin Hsu ,  Yuan-Fu Lan ,  Hsien-Wen Hsu

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/552 ,  H01L23/373 ,  H01L23/00 ,  H01L21/56

Abstract: A stacked package structure has a metal casing, a stacked chipset, an encapsulation and a redistribution layer. The stacked chipset is adhered in the metal casing. The encapsulation is formed in the metal casing to encapsulate the stacked chip set, but a plurality of surfaces of the metal pads are exposed through the encapsulation. The redistribution layer is further formed on the encapsulation and electrically connects to the metal pads of the stacked chipset. Therefore, the stacked package structure includes the metal casing, so an efficiency of heat dissipation and structural strength are increased.

公开(公告)号：US10224254B2

公开(公告)日：2019-03-05

申请号：US15497219

申请日：2017-04-26

Applicant: POWERTECH TECHNOLOGY INC.

Inventor： Ming-Chih Chen ,  Hsien-Wen Hsu ,  Yuan-Fu Lan ,  Hung-Hsin Hsu

IPC: H01L23/043 ,  H01L23/06 ,  H01L23/31 ,  H01L21/82 ,  H01L23/498 ,  H01L23/00 ,  H01L23/48

Abstract: A package structure may include a one-piece metal carrier, a die, a mold layer and a redistribution layer. The one-piece metal carrier may include a bottom portion and a first supporting structure, and the one-piece metal carrier may have a recess defined by the bottom portion and the first supporting structure. The die may be disposed in the recess of the one-piece metal carrier, and the die may have a plurality of conductive bumps. The mold layer may be formed to encapsulate the die. The mold layer may expose a portion of each of the plurality of conductive bumps and a portion of the first supporting structure. The redistribution layer may be disposed on the mold layer and electrically connected to the plurality of conductive bumps.

公开(公告)号：US20190214367A1

公开(公告)日：2019-07-11

申请号：US15867613

申请日：2018-01-10

Applicant: Powertech Technology Inc.

Inventor： Ming-Chih Chen ,  Hung-Hsin Hsu ,  Yuan-Fu Lan ,  Chi-An Wang ,  Hsien-Wen Hsu ,  Li-Chih Fang

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/28 ,  H01L23/538 ,  H01L23/552

CPC classification number: H01L25/0657 ,  H01L23/28 ,  H01L23/5384 ,  H01L23/552 ,  H01L25/50

Abstract: A stacked package has plurality of chip packages stacked on a base. Each chip package has an exterior conductive element formed on the active surface. Each exterior conductive element has a cut edge exposed on a lateral side of the chip package. The lateral trace is formed through the encapsulant and electrically connects to the cut edges of the chip packages. The base has an interconnect structure to form the electrical connection between the lateral trace and the external terminals. Therefore, the process for forming the electrical connections is simplified to enhance the reliability and the UPH for manufacturing the stacked package.

公开(公告)号：US11024603B2

公开(公告)日：2021-06-01

申请号：US16386276

申请日：2019-04-17

Applicant: POWERTECH TECHNOLOGY INC.

Inventor： Ming-Chih Chen ,  Hung-Hsin Hsu ,  Yuan-Fu Lan ,  Chi-An Wang ,  Hsien-Wen Hsu

IPC: H01L25/065 ,  H01L21/76 ,  H01L23/31 ,  H01L21/768 ,  H01L23/00 ,  H01L21/56

Abstract: A manufacturing method is applied to set a stackable chip package. The manufacturing method includes encapsulating a plurality of chips stacked with each other, disposing a lateral surface of the stacked chips having conductive elements onto a substrate, disassembling the substrate from the conductive elements when the stacked chips are encapsulated, and disposing a dielectric layer with openings on the stacked chips to align the openings with the conductive elements for ball mounting process.

公开(公告)号：US20180315674A1

公开(公告)日：2018-11-01

申请号：US15497219

申请日：2017-04-26

Applicant: POWERTECH TECHNOLOGY INC.

Inventor： Ming-Chih Chen ,  Hsien-Wen Hsu ,  Yuan-Fu Lan ,  Hung-Hsin Hsu

IPC: H01L23/043 ,  H01L23/06 ,  H01L23/31 ,  H01L21/82 ,  H01L23/48 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L23/043 ,  H01L21/82 ,  H01L23/06 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/315 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/10 ,  H01L24/11 ,  H01L2221/1068 ,  H01L2224/10 ,  H01L2224/11

Abstract: A package structure may include a one-piece metal carrier, a die, a mold layer and a redistribution layer. The one-piece metal carrier may include a bottom portion and a first supporting structure, and the one-piece metal carrier may have a recess defined by the bottom portion and the first supporting structure. The die may be disposed in the recess of the one-piece metal carrier, and the die may have a plurality of conductive bumps. The mold layer may be formed to encapsulate the die. The mold layer may expose a portion of each of the plurality of conductive bumps and a portion of the first supporting structure. The redistribution layer may be disposed on the mold layer and electrically connected to the plurality of conductive bumps.

公开(公告)号：US20190244934A1

公开(公告)日：2019-08-08

申请号：US16386276

申请日：2019-04-17

Applicant: POWERTECH TECHNOLOGY INC.

Inventor： Ming-Chih Chen ,  Hung-Hsin Hsu ,  Yuan-Fu Lan ,  Chi-An Wang ,  Hsien-Wen Hsu

IPC: H01L25/065 ,  H01L23/31 ,  H01L21/768 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L21/568 ,  H01L21/76805 ,  H01L23/3107 ,  H01L24/08 ,  H01L24/17 ,  H01L2224/02371

Abstract: A manufacturing method is applied to set a stackable chip package. The manufacturing method includes encapsulating a plurality of chips stacked with each other, disposing a lateral surface of the stacked chips having conductive elements onto a substrate, disassembling the substrate from the conductive elements when the stacked chips are encapsulated, and disposing a dielectric layer with openings on the stacked chips to align the openings with the conductive elements for ball mounting process.

公开(公告)号：US10354978B1

公开(公告)日：2019-07-16

申请号：US15867577

申请日：2018-01-10

Applicant: Powertech Technology Inc.

Inventor： Ming-Chih Chen ,  Hung-Hsin Hsu ,  Yuan-Fu Lan ,  Chi-An Wang ,  Hsien-Wen Hsu

IPC: H01L25/065 ,  H01L23/48 ,  H01L23/00 ,  H01L21/56 ,  H01L21/768 ,  H01L21/78 ,  H01L25/00

Abstract: A stacked package has plurality of chip packages stacked on active surfaces of each other, a dielectric layer, a redistribution layer and a plurality of external terminals. Each chip package has an exterior conductive element formed on the active surface. Each exterior conductive element has a cut edge exposed on at least one of the lateral side of the chip package. The dielectric layer, the redistribution layer and the external terminals are formed in sequence on the lateral side with the exposed cut edges to form the electrical connection between the cut edges, the redistribution layer and the external terminals. Therefore, the process for forming the electrical connections is simplified to enhance the reliability and the UPH for manufacturing the stacked package.

公开(公告)号：US20190214366A1

公开(公告)日：2019-07-11

申请号：US15867577

申请日：2018-01-10

Applicant: Powertech Technology Inc.

Inventor： Ming-Chih Chen ,  Hung-Hsin Hsu ,  Yuan-Fu Lan ,  Chi-An Wang ,  Hsien-Wen Hsu

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L23/48 ,  H01L21/56 ,  H01L21/768 ,  H01L21/78

CPC classification number: H01L25/0657 ,  H01L21/561 ,  H01L21/568 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/481 ,  H01L24/02 ,  H01L24/05 ,  H01L24/13 ,  H01L24/96 ,  H01L25/50 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05024 ,  H01L2224/13026 ,  H01L2224/95001 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06555 ,  H01L2225/06582

Abstract: A stacked package has plurality of chip packages stacked on active surfaces of each other, a dielectric layer, a redistribution layer and a plurality of external terminals. Each chip package has an exterior conductive element formed on the active surface. Each exterior conductive element has a cut edge exposed on at least one of the lateral side of the chip package. The dielectric layer, the redistribution layer and the external terminals are formed in sequence on the lateral side with the exposed cut edges to form the electrical connection between the cut edges, the redistribution layer and the external terminals. Therefore, the process for forming the electrical connections is simplified to enhance the reliability and the UPH for manufacturing the stacked package.