公开(公告)号：US20120052629A1

公开(公告)日：2012-03-01

申请号：US13222317

申请日：2011-08-31

Applicant: Perceval Coudrain ,  Yacine Felk ,  Patrick Lamontagne

Inventor： Perceval Coudrain ,  Yacine Felk ,  Patrick Lamontagne

IPC: H01L21/77

CPC classification number: H01L24/92 ,  H01L24/80 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05687 ,  H01L2224/32145 ,  H01L2224/80896 ,  H01L2224/80986 ,  H01L2224/83894 ,  H01L2224/9202 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01087 ,  H01L2924/14 ,  H01L2224/80895 ,  H01L2924/00

Abstract: A three-dimensional integrated structure is fabricated by assembling at least two parts together, wherein each part contains at least one metallic line covered with a covering region and having a free side. A cavity is formed in the covering region of each part, that cavity opening onto the metallic line. The two parts are joined together with the free sides facing each other and the cavities in each covering region aligned with each other. The metallic lines are then electrically joined to each other through an electromigration of the metal within at least one of the metallic lines, the electromigrated material filling the aligned cavities.

Abstract translation: 通过将至少两个部件组装在一起来制造三维一体化结构，其中每个部分包含覆盖有覆盖区域并具有自由侧的至少一个金属线。 在每个部分的覆盖区域中形成空腔，该空腔在金属线上开口。 两个部分连接在一起，自由面彼此面对，并且每个覆盖区域中的空腔彼此对准。 然后金属线通过在至少一个金属线路中的金属的电迁移彼此电连接，电解材料填充对准的空腔。

公开(公告)号：US08828797B2

公开(公告)日：2014-09-09

申请号：US13222317

申请日：2011-08-31

Applicant: Perceval Coudrain ,  Yacine Felk ,  Patrick Lamontagne

Inventor： Perceval Coudrain ,  Yacine Felk ,  Patrick Lamontagne

IPC: H01L21/77 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L24/92 ,  H01L24/80 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05687 ,  H01L2224/32145 ,  H01L2224/80896 ,  H01L2224/80986 ,  H01L2224/83894 ,  H01L2224/9202 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01087 ,  H01L2924/14 ,  H01L2224/80895 ,  H01L2924/00

Abstract: A three-dimensional integrated structure is fabricated by assembling at least two parts together, wherein each part contains at least one metallic line covered with a covering region and having a free side. A cavity is formed in the covering region of each part, that cavity opening onto the metallic line. The two parts are joined together with the free sides facing each other and the cavities in each covering region aligned with each other. The metallic lines are then electrically joined to each other through an electromigration of the metal within at least one of the metallic lines, the electromigrated material filling the aligned cavities.

Abstract translation: 通过将至少两个部件组装在一起来制造三维一体化结构，其中每个部分包含覆盖有覆盖区域并具有自由侧的至少一个金属线。 在每个部分的覆盖区域中形成空腔，该空腔在金属线上开口。 两个部分连接在一起，自由面彼此面对，并且每个覆盖区域中的空腔彼此对准。 然后金属线通过在至少一个金属线路中的金属的电迁移彼此电连接，电解材料填充对准的空腔。

公开(公告)号：US08766381B2

公开(公告)日：2014-07-01

申请号：US13230035

申请日：2011-09-12

Applicant: Fabrice Casset ,  Lionel Cadix ,  Perceval Coudrain ,  Alexis Farcy ,  Laurent-Luc Chapelon ,  Yacine Felk ,  Pascal Ancey

Inventor： Fabrice Casset ,  Lionel Cadix ,  Perceval Coudrain ,  Alexis Farcy ,  Laurent-Luc Chapelon ,  Yacine Felk ,  Pascal Ancey

IPC: H01L29/06

CPC classification number: B81C1/00246 ,  B81B2201/014 ,  B81B2201/0235 ,  B81B2201/0271 ,  B81B2203/0353 ,  B81B2207/012 ,  B81C1/005 ,  G01P15/125 ,  G01P2015/082 ,  H01L2924/0002 ,  H03H3/0073 ,  H03H9/2426 ,  H01L2924/00

Abstract: The integrated circuit comprises a support substrate having opposite first and second main surfaces. A cavity passes through the support substrate and connects the first and second main surfaces. The integrated circuit comprises a device with a mobile element, the mobile element and a pair of associated electrodes of which are included in a cavity. An anchoring node of the mobile element is located at the level of the first main surface. The integrated circuit comprises a first elementary chip arranged at the level of the first main surface and electrically connected to the device with a mobile element.

Abstract translation: 集成电路包括具有相对的第一和第二主表面的支撑基板。 空腔通过支撑基板并连接第一和第二主表面。 集成电路包括具有移动元件的装置，移动元件和一对相关联的电极包括在空腔中。 移动元件的锚定节点位于第一主表面的水平面上。 集成电路包括布置在第一主表面的电平处的第一基本芯片，并与移动元件电连接到该装置。

公开(公告)号：US20120074527A1

公开(公告)日：2012-03-29

申请号：US13230035

申请日：2011-09-12

Applicant: Fabrice Casset ,  Lionel Cadix ,  Perceval Coudrain ,  Alexis Farcy ,  Laúrent-Lüc Chapelon ,  Yacine Felk ,  Pascal Ancey

Inventor： Fabrice Casset ,  Lionel Cadix ,  Perceval Coudrain ,  Alexis Farcy ,  Laúrent-Lüc Chapelon ,  Yacine Felk ,  Pascal Ancey

IPC: H01L29/06 ,  H01L21/283

CPC classification number: B81C1/00246 ,  B81B2201/014 ,  B81B2201/0235 ,  B81B2201/0271 ,  B81B2203/0353 ,  B81B2207/012 ,  B81C1/005 ,  G01P15/125 ,  G01P2015/082 ,  H01L2924/0002 ,  H03H3/0073 ,  H03H9/2426 ,  H01L2924/00

Abstract: The integrated circuit comprises a support substrate having opposite first and second main surfaces. A cavity passes through the support substrate and connects the first and second main surfaces. The integrated circuit comprises a device with a mobile element, the mobile element and a pair of associated electrodes of which are included in a cavity. An anchoring node of the mobile element is located at the level of the first main surface. The integrated circuit comprises a first elementary chip arranged at the level of the first main surface and electrically connected to the device with a mobile element.

Abstract translation: 集成电路包括具有相对的第一和第二主表面的支撑基板。 空腔通过支撑基板并连接第一和第二主表面。 集成电路包括具有移动元件的装置，移动元件和一对相关联的电极包括在空腔中。 移动元件的锚定节点位于第一主表面的水平面上。 集成电路包括布置在第一主表面的电平处的第一基本芯片，并与移动元件电连接到该装置。

公开(公告)号：US20100308411A1

公开(公告)日：2010-12-09

申请号：US12794092

申请日：2010-06-04

Applicant: Perceval Coudrain ,  Philippe Coronel ,  Nicolas Buffet

Inventor： Perceval Coudrain ,  Philippe Coronel ,  Nicolas Buffet

IPC: H01L27/088 ,  H01L21/28

CPC classification number: H01L21/8221 ,  H01L27/0688 ,  H01L2924/00011 ,  H01L2224/80001

Abstract: A method for forming a level of a tridimensional structure on a first support in which components are formed, including the steps of forming, on a second semiconductor support, a single-crystal semiconductor substrate with an interposed thermal oxide layer; placing the free surface of the single-crystal semiconductor substrate on the upper surface of the first support; eliminating the second semiconductor support; and thinning down the thermal oxide layer down to a thickness capable of forming a gate insulator.

Abstract translation: 一种用于在其上形成部件的第一支撑件上形成三维结构水平的方法，包括以下步骤：在第二半导体支架上形成具有插入的热氧化物层的单晶半导体衬底; 将单晶半导体衬底的自由表面放置在第一支撑件的上表面上; 消除了第二个半导体支持; 并将热氧化层减薄至能够形成栅极绝缘体的厚度。

公开(公告)号：US08456258B2

公开(公告)日：2013-06-04

申请号：US12783095

申请日：2010-05-19

Applicant: Perceval Coudrain ,  David Petit

Inventor： Perceval Coudrain ,  David Petit

IPC: H03H9/54

CPC classification number: H03H9/173 ,  H03H3/04 ,  H03H2003/021 ,  Y10T29/42

Abstract: A resonant device including a stack of a first metal layer, a piezoelectric material layer, and a second metal layer formed on a silicon substrate, a cavity being formed in depth in the substrate, the thickness of the silicon above the cavity having at least a first value in a first region located opposite to the center of the stack, having a second value in a second region located under the periphery of the stack and having at least a third value in a third region surrounding the second region, the second value being greater than the first and the third values.

Abstract translation: 一种谐振装置，包括第一金属层，压电材料层和形成在硅衬底上的第二金属层的堆叠，空腔在衬底中深度形成，空腔上方的硅的厚度至少具有 第一值位于与堆叠的中心相对的第一区域中，在位于堆叠的周边下方的第二区域中具有第二值，并且在围绕第二区域的第三区域中具有至少第三值，第二值为 大于第一和第三值。

公开(公告)号：US20080205027A1

公开(公告)日：2008-08-28

申请号：US12035297

申请日：2008-02-21

Applicant: Philippe Coronel ,  Perceval Coudrain ,  Pascale Mazoyer

Inventor： Philippe Coronel ,  Perceval Coudrain ,  Pascale Mazoyer

IPC: H01R9/00 ,  H05K7/00

CPC classification number: H01L25/50 ,  H01L24/80 ,  H01L24/92 ,  H01L25/0657 ,  H01L2224/05571 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80907 ,  H01L2224/80986 ,  H01L2224/9202 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/01037 ,  H01L2924/01079 ,  Y10T29/49149 ,  H01L2924/00012 ,  H01L2224/05552

Abstract: A process for assembling two parts of an integrated electronic circuit has two successive steps. During a first step, the two circuit parts are made into a single unit by molecular bonding, realized on respective application surfaces of the two parts. During a second step, electrical connections are formed from connection portions already present in the application surfaces of the two circuit parts. The connections formed extend across the bonding interface, and are compatible with a high reliability and a high level of integration of the circuit.

Abstract translation: 用于组装集成电子电路的两部分的过程具有两个连续的步骤。 在第一步骤期间，两个电路部分通过分子键合制成单个单元，实现在两个部分的各个应用表面上。 在第二步骤期间，电连接由已经存在于两个电路部分的应用表面中的连接部分形成。 所形成的连接跨越接合界面，并且与电路的高可靠性和高集成度兼容。

公开(公告)号：US08186568B2

公开(公告)日：2012-05-29

申请号：US12035297

申请日：2008-02-21

Applicant: Philippe Coronel ,  Perceval Coudrain ,  Pascale Mazoyer

Inventor： Philippe Coronel ,  Perceval Coudrain ,  Pascale Mazoyer

IPC: B23K31/02

CPC classification number: H01L25/50 ,  H01L24/80 ,  H01L24/92 ,  H01L25/0657 ,  H01L2224/05571 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80907 ,  H01L2224/80986 ,  H01L2224/9202 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/01037 ,  H01L2924/01079 ,  Y10T29/49149 ,  H01L2924/00012 ,  H01L2224/05552

Abstract: A process for assembling two parts of an integrated electronic circuit has two successive steps. During a first step, the two circuit parts are made into a single unit by molecular bonding, realized on respective application surfaces of the two parts. During a second step, electrical connections are formed from connection portions already present in the application surfaces of the two circuit parts. The connections formed extend across the bonding interface, and are compatible with a high reliability and a high level of integration of the circuit.

Abstract translation: 用于组装集成电子电路的两部分的过程具有两个连续的步骤。 在第一步骤期间，两个电路部分通过分子键合制成单个单元，实现在两个部分的各个应用表面上。 在第二步骤期间，电连接由已经存在于两个电路部分的应用表面中的连接部分形成。 所形成的连接跨越接合界面，并且与电路的高可靠性和高集成度兼容。

公开(公告)号：US20100295631A1

公开(公告)日：2010-11-25

申请号：US12783095

申请日：2010-05-19

Applicant: Perceval Coudrain ,  David Petit

Inventor： Perceval Coudrain ,  David Petit

IPC: H03H9/17 ,  H01L41/22

CPC classification number: H03H9/173 ,  H03H3/04 ,  H03H2003/021 ,  Y10T29/42

Abstract: A resonant device including a stack of a first metal layer, a piezoelectric material layer, and a second metal layer formed on a silicon substrate, a cavity being formed in depth in the substrate, the thickness of the silicon above the cavity having at least a first value in a first region located opposite to the center of the stack, having a second value in a second region located under the periphery of the stack and having at least a third value in a third region surrounding the second region, the second value being greater than the first and the third values.

Abstract translation: 一种谐振装置，包括第一金属层，压电材料层和形成在硅衬底上的第二金属层的堆叠，空腔在衬底中深度形成，空腔上方的硅的厚度至少具有 第一值位于与堆叠的中心相对的第一区域中，在位于堆叠的周边下方的第二区域中具有第二值，并且在围绕第二区域的第三区域中具有至少第三值，第二值为 大于第一和第三值。

公开(公告)号：US20090256224A1

公开(公告)日：2009-10-15

申请号：US12398872

申请日：2009-03-05

Applicant: Perceval Coudrain ,  Philippe Coronel ,  Michel Marty ,  Matthieu Bopp

Inventor： Perceval Coudrain ,  Philippe Coronel ,  Michel Marty ,  Matthieu Bopp

IPC: H01L31/0232 ,  H01L31/18

CPC classification number: H01L27/14625 ,  H01L27/14645 ,  H01L27/14683 ,  H01L31/0232

Abstract: A semiconductor structure including a first active area under which is buried a first reflective layer and a least one second active area under which is buried a second reflective layer, wherein the upper surface of the second reflective layer is closer to the upper surface of the structure than the upper surface of the first reflective layer.

Abstract translation: 一种半导体结构，包括第一有源区，其下埋有第一反射层和至少一个第二有源区，在该第一有源区内掩埋有第二反射层，其中第二反射层的上表面更靠近该结构的上表面 比第一反射层的上表面。