公开(公告)号：US12149686B2

公开(公告)日：2024-11-19

申请号：US18296272

申请日：2023-04-05

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Ryuichi Kanoh ,  Takahiro Nishi ,  Tadamasa Toma

IPC: H04N19/117 ,  H04N19/14 ,  H04N19/159 ,  H04N19/174

Abstract: An encoder includes processing circuitry and a memory coupled to the processing circuitry. The processing circuitry is configured to: select a filter based at least on a prediction mode used for a first block, the filter including first filter coefficients for the first block and second filter coefficients for a second block; multiply values of first pixels among the first block and second pixels among the second block by the first filter coefficients to change a value of a first pixel in the first pixels; and multiply the values of the first pixels among the first block and the second pixels among the second block by the second filter coefficients to change a value of a second pixel in the second pixels.

公开(公告)号：US12137236B2

公开(公告)日：2024-11-05

申请号：US18235960

申请日：2023-08-21

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Virginie Drugeon ,  Tadamasa Toma ,  Takahiro Nishi ,  Kiyofumi Abe ,  Ryuichi Kanoh

IPC: H04N19/189 ,  H04N19/105 ,  H04N19/132 ,  H04N19/159 ,  H04N19/182

Abstract: An encoder includes circuitry and memory. The circuitry, using the memory: derives a one-dimensional array of a plurality of reference samples for intra prediction; performs smoothing on the one-dimensional array of the plurality of reference samples which has been derived; and generates a prediction image using the plurality of reference samples. In deriving the one-dimensional array, the circuitry projects a value of at least one decoded pixel located on a first line onto a second line perpendicular to the first line, to derive at least one of the plurality of reference samples, and the smoothing is performed on the at least one decoded pixel projected onto the second line.

公开(公告)号：US12088802B2

公开(公告)日：2024-09-10

申请号：US17876925

申请日：2022-07-29

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Ryuichi Kanoh ,  Tadamasa Toma ,  Kiyofumi Abe ,  Takahiro Nishi

IPC: H04N19/119 ,  H04N19/176

CPC classification number: H04N19/119 ,  H04N19/176

Abstract: An encoder includes circuitry and memory coupled to the circuitry. The circuitry in operation: determines whether the shape of a current chroma block to be split satisfies a first condition; generates one or more second candidates for a block partitioning method by eliminating one or more predetermined candidates from a plurality of first candidates for a block partitioning method when the current chroma block satisfies the first condition; selects a block partitioning method from among the one or more second candidates; and splits the current chroma block according to the block partitioning method selected.

公开(公告)号：US11997310B2

公开(公告)日：2024-05-28

申请号：US18109435

申请日：2023-02-14

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi Abe ,  Takahiro Nishi ,  Tadamasa Toma ,  Ryuichi Kanoh

IPC: H04N19/537 ,  H04N19/105 ,  H04N19/157 ,  H04N19/52 ,  H04N19/573

CPC classification number: H04N19/537 ,  H04N19/105 ,  H04N19/157 ,  H04N19/52 ,  H04N19/573

Abstract: An encoder includes memory and circuitry. The circuitry derives a first motion vector in a unit of a prediction block using a first inter frame prediction mode that uses a degree of matching between two reconstructed images of two regions in two difference pictures, the prediction block being obtained by splitting an image included in a video; and performs, in the unit of the prediction block, a first motion compensation process that generates a prediction image by referring to a spatial gradient of luminance in an image generated by performing motion compensation using the first motion vector derived.

公开(公告)号：US11909968B2

公开(公告)日：2024-02-20

申请号：US17726133

申请日：2022-04-21

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi Abe ,  Takahiro Nishi ,  Tadamasa Toma ,  Ryuichi Kanoh ,  Chong Soon Lim ,  Ru Ling Liao ,  Hai Wei Sun ,  Sughosh Pavan Shashidhar ,  Han Boon Teo ,  Jing Ya Li

IPC: H04N19/52 ,  H04N19/119 ,  H04N19/137 ,  H04N19/176

CPC classification number: H04N19/119 ,  H04N19/137 ,  H04N19/176 ,  H04N19/52

Abstract: Provided is an encoder which includes circuitry and memory. Using the memory, the circuitry splits an image block into a plurality of partitions, obtains a prediction image for a partition, and encodes the image block using the prediction image. When the partition is not a non-rectangular partition, the circuitry obtains (i) a first prediction image for the partition, (ii) a gradient image for the first prediction image, and (iii) a second prediction image as the prediction image using the first prediction image and the gradient image. When the partition is a non-rectangular partition, the circuitry obtains the first prediction image as the prediction image without using the gradient image.

公开(公告)号：US11895298B2

公开(公告)日：2024-02-06

申请号：US17724178

申请日：2022-04-19

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi Abe ,  Takahiro Nishi ,  Tadamasa Toma ,  Ryuichi Kanoh ,  Chong Soon Lim ,  Ru Ling Liao ,  Hai Wei Sun ,  Sughosh Pavan Shashidhar ,  Han Boon Teo ,  Jing Ya Li

IPC: H04N19/52 ,  H04N19/119 ,  H04N19/137 ,  H04N19/176

CPC classification number: H04N19/119 ,  H04N19/137 ,  H04N19/176 ,  H04N19/52

Abstract: Provided is an encoder which includes circuitry and memory. Using the memory, the circuitry splits an image block into a plurality of partitions, obtains a prediction image for a partition, and encodes the image block using the prediction image. When the partition is not a non-rectangular partition, the circuitry obtains (i) a first prediction image for the partition, (ii) a gradient image for the first prediction image, and (iii) a second prediction image as the prediction image using the first prediction image and the gradient image. When the partition is a non-rectangular partition, the circuitry obtains the first prediction image as the prediction image without using the gradient image.

公开(公告)号：US11889075B2

公开(公告)日：2024-01-30

申请号：US17726125

申请日：2022-04-21

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi Abe ,  Takahiro Nishi ,  Tadamasa Toma ,  Ryuichi Kanoh ,  Chong Soon Lim ,  Ru Ling Liao ,  Hai Wei Sun ,  Sughosh Pavan Shashidhar ,  Han Boon Teo ,  Jing Ya Li

IPC: H04N19/119 ,  H04N19/176

CPC classification number: H04N19/119 ,  H04N19/176

Abstract: Provided is an encoder which includes circuitry and memory. The circuitry encodes an image block using the memory. In encoding the image block, the circuitry: obtains one or more size parameters related to a size of the image block; determines whether the one or more size parameters and one or more thresholds satisfy a determined relationship; encodes a split parameter when the one or more size parameters and the one or more thresholds are determined to satisfy the determined relationship, the split parameter indicating whether the image block is to be split into a plurality of partitions including a non-rectangular partition; and encodes the image block after splitting the image block into the plurality of partitions when the split parameter indicates that the image block is to be split into the plurality of partitions.

公开(公告)号：US11876963B2

公开(公告)日：2024-01-16

申请号：US17725113

申请日：2022-04-20

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi Abe ,  Takahiro Nishi ,  Tadamasa Toma ,  Ryuichi Kanoh ,  Chong Soon Lim ,  Ru Ling Liao ,  Hai Wei Sun ,  Sughosh Pavan Shashidhar ,  Han Boon Teo ,  Jing Ya Li

IPC: H04N19/119 ,  H04N19/176

CPC classification number: H04N19/119 ,  H04N19/176

Abstract: Provided is an encoder which includes circuitry and memory. The circuitry encodes an image block using the memory. In encoding the image block, the circuitry: obtains one or more size parameters related to a size of the image block; determines whether the one or more size parameters and one or more thresholds satisfy a determined relationship; encodes a split parameter when the one or more size parameters and the one or more thresholds are determined to satisfy the determined relationship, the split parameter indicating whether the image block is to be split into a plurality of partitions including a non-rectangular partition; and encodes the image block after splitting the image block into the plurality of partitions when the split parameter indicates that the image block is to be split into the plurality of partitions.

公开(公告)号：US11863741B2

公开(公告)日：2024-01-02

申请号：US17368442

申请日：2021-07-06

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Ryuichi Kanoh ,  Takahiro Nishi ,  Tadamasa Toma

IPC: H04N19/117 ,  H04N19/176 ,  H04N19/182 ,  H04N19/186

CPC classification number: H04N19/117 ,  H04N19/176 ,  H04N19/182 ,  H04N19/186

Abstract: An encoder includes processing circuitry and a memory coupled to the processing circuitry. Using the memory, the processing circuitry is configured to: change values of pixels in a first block and a second block to filter a boundary between the first block and the second block. The pixels include type one pixels and type two pixels different from the type one pixels. The first set of filter coefficients applied to the type one pixels in the first block and the second set of filter coefficients applied to the type one pixels in the second block are selected to be asymmetrical with respect to the boundary based on block sizes of the first block and the second block.

公开(公告)号：US11856192B2

公开(公告)日：2023-12-26

申请号：US18149525

申请日：2023-01-03

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Ryuichi Kanoh ,  Takahiro Nishi ,  Tadamasa Toma ,  Kiyofumi Abe

IPC: H04N19/117 ,  H04N19/146 ,  H04N19/176

CPC classification number: H04N19/117 ,  H04N19/146 ,  H04N19/176

Abstract: A decoder comprises circuitry and memory. The circuitry, using the memory, in operation, determines a number of first pixels and a number of second pixels used in a deblocking filter process, wherein the first pixels are located at an upper side of a block boundary and the second pixels are located at a lower side of the block boundary, and performs the deblocking filter process on the block boundary. The number of the first pixels and the number of the second pixels are selected from among candidates, wherein the candidates include at least 4 and M larger than 4. Response to a location of the block boundary being a predetermined location, the number of the first pixels used in the deblocking filter process is limited to be 4.