公开(公告)号：US20170256471A1

公开(公告)日：2017-09-07

申请号：US15432932

申请日：2017-02-15

Applicant: POWERTECH TECHNOLOGY INC.

Inventor： Li-Chih Fang ,  Chia-Chang Chang ,  Hung-Hsin Hsu ,  Wen-Hsiung Chang ,  Kee-Wei Chung ,  Chia-Wen Lien

IPC: H01L23/31 ,  H01L23/00 ,  H01L27/146 ,  H01L21/56 ,  H01L21/768 ,  H01L23/48 ,  H01L23/498

CPC classification number: H01L23/3114 ,  H01L21/56 ,  H01L21/76898 ,  H01L23/3121 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/562 ,  H01L24/03 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/32 ,  H01L24/83 ,  H01L27/14618 ,  H01L27/14627 ,  H01L27/14632 ,  H01L27/14636 ,  H01L2224/0237 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/1134 ,  H01L2224/11462 ,  H01L2224/13016 ,  H01L2224/13027 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2924/0132 ,  H01L2924/15311

Abstract: A wafer level chip scale package (WLCSP) has a device chip, a carrier chip, an offset pad, a conductive spacing bump and a through hole via (THV). The device chip is attached to the carrier chip. The offset pad is disposed on a first surface of the device chip. The conductive spacing bump is formed on the offset pad. The through hole via includes a through hole and a hole metal layer. The through hole penetrates through the carrier chip and the device chip, and the hole metal layer is formed in the through hole and in contact with the offset pad.

公开(公告)号：US09972554B2

公开(公告)日：2018-05-15

申请号：US15432932

申请日：2017-02-15

Applicant: POWERTECH TECHNOLOGY INC.

Inventor： Li-Chih Fang ,  Chia-Chang Chang ,  Hung-Hsin Hsu ,  Wen-Hsiung Chang ,  Kee-Wei Chung ,  Chia-Wen Lien

IPC: H01L29/40 ,  H01L23/52 ,  H01L23/48 ,  H01L23/31 ,  H01L21/56 ,  H01L21/768 ,  H01L23/498 ,  H01L23/00 ,  H01L27/146

CPC classification number: H01L23/3114 ,  H01L21/56 ,  H01L21/76898 ,  H01L23/3121 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/562 ,  H01L24/03 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/32 ,  H01L24/83 ,  H01L27/14618 ,  H01L27/14627 ,  H01L27/14632 ,  H01L27/14636 ,  H01L2224/0237 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/1134 ,  H01L2224/11462 ,  H01L2224/13016 ,  H01L2224/13027 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2924/0132 ,  H01L2924/15311

Abstract: A wafer level chip scale package (WLCSP) has a device chip, a carrier chip, an offset pad, a conductive spacing bump and a through hole via (THV). The device chip is attached to the carrier chip. The offset pad is disposed on a first surface of the device chip. The conductive spacing bump is formed on the offset pad. The through hole via includes a through hole and a hole metal layer. The through hole penetrates through the carrier chip and the device chip, and the hole metal layer is formed in the through hole and in contact with the offset pad.