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公开(公告)号：US20200035306A1
公开(公告)日：2020-01-30
申请号：US16120313
申请日：2018-09-03
Applicant: PHISON ELECTRONICS CORP.
Inventor： Wei Lin , Yu-Cheng Hsu , Tsai-Hao Kuo , Szu-Wei Chen , Lih Yuarn Ou , Hsiao-Yi Lin
Abstract: A voltage adjusting method, a memory controlling circuit unit and a memory storage device are provided. The method includes: reading a first physical programming unit in a first physical programming unit group to obtain first data; correcting the first data according to a first error check and correction code corresponding to the first data to obtain first corrected data; reading a second physical programming unit in the first physical programming unit group to obtain second data; and adjusting a first read voltage for reading a first memory cell to a second read voltage according to the first data, the first corrected data, and the second data.
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公开(公告)号：US20210397347A1
公开(公告)日：2021-12-23
申请号：US16921874
申请日：2020-07-06
Applicant: PHISON ELECTRONICS CORP.
Inventor： Wei Lin , Yu-Cheng Hsu , Hsiao-Yi Lin , Yu-Siang Yang
IPC: G06F3/06
Abstract: A data protection method, a memory storage device and a memory control circuit unit are provided. The method includes: setting a plurality of disk array tags corresponding to a plurality of word lines and a plurality of memory planes, and the plurality of disk array tags corresponding to one of the word lines connected to one of the memory planes are at least partially identical to the plurality of disk array tags corresponding to another one of the word lines connected to another one of the memory planes; receiving a write command and data corresponding to the write command from a host system; and sequentially writing the data into the plurality of word lines and the plurality of memory planes corresponding to the plurality of disk array tags.
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公开(公告)号：US20200379654A1
公开(公告)日：2020-12-03
申请号：US16529807
申请日：2019-08-02
Applicant: PHISON ELECTRONICS CORP.
Inventor： Wei Lin , Yu-Cheng Hsu , Hsiao-Yi Lin , Yu-Siang Yang
Abstract: A memory control method, a memory storage device and a memory control circuit unit are provided. The method includes: reading a first physical unit among a plurality of physical units based on a first electrical configuration to obtain first soft information; reading the first physical unit based on a second electrical configuration which is different from the first electrical configuration to obtain second soft information; classifying a plurality of memory cells in the first physical unit according to the first soft information and the second soft information; and decoding data read from the first physical unit according to a classification result of the memory cells.
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公开(公告)号：US11573704B2
公开(公告)日：2023-02-07
申请号：US16529807
申请日：2019-08-02
Applicant: PHISON ELECTRONICS CORP.
Inventor： Wei Lin , Yu-Cheng Hsu , Hsiao-Yi Lin , Yu-Siang Yang
Abstract: A memory control method, a memory storage device and a memory control circuit unit are provided. The method includes: reading a first physical unit among a plurality of physical units based on a first electrical configuration to obtain first soft information; reading the first physical unit based on a second electrical configuration which is different from the first electrical configuration to obtain second soft information; classifying a plurality of memory cells in the first physical unit according to the first soft information and the second soft information; and decoding data read from the first physical unit according to a classification result of the memory cells.
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公开(公告)号：US12148486B2
公开(公告)日：2024-11-19
申请号：US18181546
申请日：2023-03-10
Applicant: PHISON ELECTRONICS CORP.
Inventor： Hsiao-Yi Lin , Shih-Jia Zeng , Chen Yang Tang , Shi-Chieh Hsu , Wei Lin
Abstract: A read voltage adjustment method, a memory storage device, and a memory control circuit unit are disclosed. The method includes: sending a write command sequence instructing to program a plurality of first memory cells in a rewritable non-volatile memory module; sending a first read command sequence instructing to read the programmed first memory cells using a first read voltage level to obtain first count information; obtaining first compensation information corresponding to the first read voltage level, wherein the first compensation information reflects a deviation in evenly programming the first memory cells to a plurality of states; and adjusting the first read voltage level according to the first count information, the first compensation information, and default count information corresponding to the first read voltage level.
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Patent Agency Ranking
6.发明公开公开(公告)号：US20230214150A1
公开(公告)日：2023-07-06
申请号：US17679109
申请日：2022-02-24
Applicant: PHISON ELECTRONICS CORP.
Inventor： Shih-Jia Zeng , Chun-Wei Tsao , Hsiao-Yi Lin , Wei Lin
IPC: G06F3/06
CPC classification number: G06F3/0655 , G06F3/0604 , G06F3/0679
Abstract: A read voltage level correction method, a memory storage device, and a memory control circuit unit are provided. The method includes: using a first read voltage level as an initial read voltage level to perform a first data read operation on a first physical unit among multiple physical units to obtain a second read voltage level used to successfully read the first physical unit; recording association information between the first read voltage level and the second read voltage level in a transient look-up table; and performing a second data read operation according to a read level tracking table and the association information recorded in the transient look-up table.
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公开(公告)号：US10679707B2
公开(公告)日：2020-06-09
申请号：US16120313
申请日：2018-09-03
Applicant: PHISON ELECTRONICS CORP.
Inventor： Wei Lin , Yu-Cheng Hsu , Tsai-Hao Kuo , Szu-Wei Chen , Lih Yuarn Ou , Hsiao-Yi Lin
Abstract: A voltage adjusting method, a memory controlling circuit unit and a memory storage device are provided. The method includes: reading a first physical programming unit in a first physical programming unit group to obtain first data; correcting the first data according to a first error check and correction code corresponding to the first data to obtain first corrected data; reading a second physical programming unit in the first physical programming unit group to obtain second data; and adjusting a first read voltage for reading a first memory cell to a second read voltage according to the first data, the first corrected data, and the second data.
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公开(公告)号：US20240265983A1
公开(公告)日：2024-08-08
申请号：US18181546
申请日：2023-03-10
Applicant: PHISON ELECTRONICS CORP.
Inventor： Hsiao-Yi Lin , Shih-Jia Zeng , Chen Yang Tang , Shi-Chieh Hsu , Wei Lin
CPC classification number: G11C16/3459 , G11C16/102 , G11C16/26 , G11C16/3404
Abstract: A read voltage adjustment method, a memory storage device, and a memory control circuit unit are disclosed. The method includes: sending a write command sequence instructing to program a plurality of first memory cells in a rewritable non-volatile memory module; sending a first read command sequence instructing to read the programmed first memory cells using a first read voltage level to obtain first count information; obtaining first compensation information corresponding to the first read voltage level, wherein the first compensation information reflects a deviation in evenly programming the first memory cells to a plurality of states; and adjusting the first read voltage level according to the first count information, the first compensation information, and default count information corresponding to the first read voltage level.
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9.发明授权公开(公告)号：US11972139B2
公开(公告)日：2024-04-30
申请号：US17679109
申请日：2022-02-24
Applicant: PHISON ELECTRONICS CORP.
Inventor： Shih-Jia Zeng , Chun-Wei Tsao , Hsiao-Yi Lin , Wei Lin
CPC classification number: G06F3/0655 , G06F3/0604 , G06F3/0679 , G11C16/26 , G11C29/021 , G11C29/028
Abstract: A read voltage level correction method, a memory storage device, and a memory control circuit unit are provided. The method includes: using a first read voltage level as an initial read voltage level to perform a first data read operation on a first physical unit among multiple physical units to obtain a second read voltage level used to successfully read the first physical unit; recording association information between the first read voltage level and the second read voltage level in a transient look-up table; and performing a second data read operation according to a read level tracking table and the association information recorded in the transient look-up table.
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10.发明授权公开(公告)号：US11604586B2
公开(公告)日：2023-03-14
申请号：US16921874
申请日：2020-07-06
Applicant: PHISON ELECTRONICS CORP.
Inventor： Wei Lin , Yu-Cheng Hsu , Hsiao-Yi Lin , Yu-Siang Yang
IPC: G06F3/06
Abstract: A data protection method, a memory storage device and a memory control circuit unit are provided. The method includes: setting a plurality of disk array tags corresponding to a plurality of word lines and a plurality of memory planes, and the plurality of disk array tags corresponding to one of the word lines connected to one of the memory planes are at least partially identical to the plurality of disk array tags corresponding to another one of the word lines connected to another one of the memory planes; receiving a write command and data corresponding to the write command from a host system; and sequentially writing the data into the plurality of word lines and the plurality of memory planes corresponding to the plurality of disk array tags.
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