公开(公告)号：US20240128987A1

公开(公告)日：2024-04-18

申请号：US17994399

申请日：2022-11-28

Applicant: PHISON ELECTRONICS CORP.

Inventor： Shih-Jia Zeng ,  Yi-Fang Chang ,  Chun-Wei Tsao ,  Chen-An Hsu ,  Wei Lin

IPC: H03M13/15 ,  H03M13/01

CPC classification number: H03M13/1555 ,  H03M13/015 ,  H03M13/1575

Abstract: A decoding method, a memory storage device and a memory control circuit unit are disclosed. The method includes: activating a decoding circuit which supports a plurality of decoding modes each corresponding to a threshold value, wherein a distribution of the threshold value corresponds to error correction abilities of the decoding modes; reading first data from a rewritable non-volatile memory module; performing, by the decoding circuit, a first decoding operation on the first data; obtaining a decoding parameter according to an execution result of the first decoding operation; and performing, by the decoding circuit, a second decoding operation on the first data based on a first decoding mode among the decoding modes according to a relative numerical relationship between the decoding parameter and the threshold value.

公开(公告)号：US20220107756A1

公开(公告)日：2022-04-07

申请号：US17080854

申请日：2020-10-27

Applicant: PHISON ELECTRONICS CORP.

Inventor： Shih-Jia Zeng ,  Chun-Wei Tsao ,  Chih-Wei Wang ,  Wei Lin

IPC: G06F3/06

Abstract: An exemplary embodiment of the invention provides a read voltage control method for a rewritable non-volatile memory module. The method includes: sending a first read command sequence which instructs a reading of a plurality of first memory cells by using a first voltage level to obtain first data; obtaining first adjustment information of a read voltage according to the first data and a channel parameter of the first memory cells, and the channel parameter reflects a channel status of the first memory cells; and adjusting a voltage level of the read voltage from the first voltage level to a second voltage level according to the first adjustment information.

公开(公告)号：US20230214150A1

公开(公告)日：2023-07-06

申请号：US17679109

申请日：2022-02-24

Applicant: PHISON ELECTRONICS CORP.

Inventor： Shih-Jia Zeng ,  Chun-Wei Tsao ,  Hsiao-Yi Lin ,  Wei Lin

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679

Abstract: A read voltage level correction method, a memory storage device, and a memory control circuit unit are provided. The method includes: using a first read voltage level as an initial read voltage level to perform a first data read operation on a first physical unit among multiple physical units to obtain a second read voltage level used to successfully read the first physical unit; recording association information between the first read voltage level and the second read voltage level in a transient look-up table; and performing a second data read operation according to a read level tracking table and the association information recorded in the transient look-up table.

公开(公告)号：US12008262B2

公开(公告)日：2024-06-11

申请号：US17080854

申请日：2020-10-27

Applicant: PHISON ELECTRONICS CORP.

Inventor： Shih-Jia Zeng ,  Chun-Wei Tsao ,  Chih-Wei Wang ,  Wei Lin

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679

Abstract: An exemplary embodiment of the invention provides a read voltage control method for a rewritable non-volatile memory module. The method includes: sending a first read command sequence which instructs a reading of a plurality of first memory cells by using a first voltage level to obtain first data; obtaining first adjustment information of a read voltage according to the first data and a channel parameter of the first memory cells, and the channel parameter reflects a channel status of the first memory cells; and adjusting a voltage level of the read voltage from the first voltage level to a second voltage level according to the first adjustment information.

公开(公告)号：US11972139B2

公开(公告)日：2024-04-30

申请号：US17679109

申请日：2022-02-24

Applicant: PHISON ELECTRONICS CORP.

Inventor： Shih-Jia Zeng ,  Chun-Wei Tsao ,  Hsiao-Yi Lin ,  Wei Lin

IPC: G11C16/26 ,  G06F3/06 ,  G11C29/02

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679 ,  G11C16/26 ,  G11C29/021 ,  G11C29/028

Abstract: A read voltage level correction method, a memory storage device, and a memory control circuit unit are provided. The method includes: using a first read voltage level as an initial read voltage level to perform a first data read operation on a first physical unit among multiple physical units to obtain a second read voltage level used to successfully read the first physical unit; recording association information between the first read voltage level and the second read voltage level in a transient look-up table; and performing a second data read operation according to a read level tracking table and the association information recorded in the transient look-up table.

公开(公告)号：US11962328B1

公开(公告)日：2024-04-16

申请号：US17994399

申请日：2022-11-28

Applicant: PHISON ELECTRONICS CORP.

Inventor： Shih-Jia Zeng ,  Yi-Fang Chang ,  Chun-Wei Tsao ,  Chen-An Hsu ,  Wei Lin

IPC: H03M13/00 ,  H03M13/01 ,  H03M13/15

CPC classification number: H03M13/1555 ,  H03M13/015 ,  H03M13/1575

Abstract: A decoding method, a memory storage device and a memory control circuit unit are disclosed. The method includes: activating a decoding circuit which supports a plurality of decoding modes each corresponding to a threshold value, wherein a distribution of the threshold value corresponds to error correction abilities of the decoding modes; reading first data from a rewritable non-volatile memory module; performing, by the decoding circuit, a first decoding operation on the first data; obtaining a decoding parameter according to an execution result of the first decoding operation; and performing, by the decoding circuit, a second decoding operation on the first data based on a first decoding mode among the decoding modes according to a relative numerical relationship between the decoding parameter and the threshold value.