公开(公告)号：US20050189962A1

公开(公告)日：2005-09-01

申请号：US10783886

申请日：2004-02-20

申请人： Om Agrawal ,  Howard Tang ,  Jack Wong

发明人： Om Agrawal ,  Howard Tang ,  Jack Wong

IPC分类号： H03K19/177

CPC分类号： H03K19/17772 ,  H03K19/17732 ,  H03K19/1776 ,  H03K19/17768

摘要： Programmable logic devices and techniques for programming and/or reconfiguring these devices are disclosed. For example, in accordance with an embodiment of the present invention, a programmable logic device is disclosed that incorporates flash memory and SRAM and includes multiple data ports for programming the flash memory and/or the SRAM.

摘要翻译： 公开了用于编程和/或重新配置这些设备的可编程逻辑器件和技术。 例如，根据本发明的实施例，公开了一种可编程逻辑器件，其包括闪速存储器和SRAM，并且包括用于对闪速存储器和/或SRAM进行编程的多个数据端口。

公开(公告)号：US20060232295A1

公开(公告)日：2006-10-19

申请号：US11455315

申请日：2006-06-16

申请人： Om Agrawal ,  Howard Tang ,  Jack Wong

发明人： Om Agrawal ,  Howard Tang ,  Jack Wong

IPC分类号： H03K19/173

CPC分类号： H03K19/17772 ,  H03K19/17732 ,  H03K19/1776 ,  H03K19/17768

摘要： Programmable logic devices and techniques for programming and/or reconfiguring these devices are disclosed. For example, in accordance with an embodiment of the present invention, a programmable logic device is disclosed that incorporates flash memory and SRAM and includes multiple data ports for programming the flash memory and/or the SRAM.

摘要翻译： 公开了用于编程和/或重新配置这些设备的可编程逻辑器件和技术。 例如，根据本发明的实施例，公开了一种可编程逻辑器件，其包括闪速存储器和SRAM，并且包括用于对闪速存储器和/或SRAM进行编程的多个数据端口。

公开(公告)号：US08112656B1

公开(公告)日：2012-02-07

申请号：US12578492

申请日：2009-10-13

申请人： Shyam Chandra ,  Om Agrawal ,  Ludmil Nikolov ,  Harald Weller ,  Douglas Morse

发明人： Shyam Chandra ,  Om Agrawal ,  Ludmil Nikolov ,  Harald Weller ,  Douglas Morse

IPC分类号： G06F1/00 ,  G06F1/04 ,  G06F1/12 ,  G06F5/06

CPC分类号： G06F1/10

摘要： In one embodiment, a clock distribution chip includes a first clock input adapted to receive a first single-ended input clock signal, a second clock input adapted to receive a second single-ended input clock signal, and input buffer circuitry coupled to the first and second clock inputs. The input buffer circuitry is adapted to select an input clock signal among the first single-ended input clock signal, the second single-ended input clock signal, and a differential input clock signal derived from the first and second single-ended input clock signals. A phase-locked loop (PLL) is adapted to receive an input clock signal selected by the input buffer circuitry and to generate a PLL clock signal based on the selected input clock signal. A clock output provides an output clock signal based on the PLL clock signal.

摘要翻译： 在一个实施例中，时钟分配芯片包括适于接收第一单端输入时钟信号的第一时钟输入，适于接收第二单端输入时钟信号的第二时钟输入以及耦合到第一和第 第二个时钟输入。 输入缓冲器电路适于在第一单端输入时钟信号，第二单端输入时钟信号和从第一和第二单端输入时钟信号导出的差分输入时钟信号之间选择输入时钟信号。 锁相环（PLL）适于接收由输入缓冲器电路选择的输入时钟信号，并且基于所选择的输入时钟信号产生PLL时钟信号。 时钟输出提供基于PLL时钟信号的输出时钟信号。

公开(公告)号：US4771285A

公开(公告)日：1988-09-13

申请号：US795159

申请日：1985-11-05

申请人： Om Agrawal ,  Kapil Shankar ,  Fares N. Mubarak

发明人： Om Agrawal ,  Kapil Shankar ,  Fares N. Mubarak

IPC分类号： H03K19/173 ,  H03K19/177 ,  H04Q1/00 ,  G06F7/38

CPC分类号： H03K19/17716

摘要： A logic circuit communicating to and from an input/output port in a variety of input modes and in a variety of output modes. The circuit may be configured to have a dedicated, registered, or latched input; and in the output mode to have a registered, combinatorial or latched output. A register/latch, in conjunction with a programmable input select multiplexer, can function as an input, output or buried register or as a transparent latch. A programmable clock select multiplexer selects between a clock/latch enable signal applied at an external pin or a product term generated internally. Clock polarity control is also provided. Asynchronous reset and preset of the register/latch is provided along with polarity control therefor. Dedicated and programmable feedback paths are provided. An output inverter can selectably be enabled from internal signals or from an external pin. The logic circuit can be deployed in banks, each bank electably receiving the same or a different clock. The register/latch can be preloaded via an internally-generated signal or from the external pins.

摘要翻译： 在各种输入模式和各种输出模式下与输入/输出端口通信的逻辑电路。 电路可以被配置为具有专用的，已注册的或锁存的输入; 并在输出模式下具有注册，组合或锁存输出。 与可编程输入选择多路复用器相结合的寄存器/锁存器可用作输入，输出或掩埋寄存器或透明锁存器。 可编程时钟选择多路复用器在外部引脚施加的时钟/锁存使能信号或内部产生的乘积项之间进行选择。 还提供时钟极性控制。 提供异步复位和寄存器/锁存器的预置以及极性控制。 提供专用和可编程的反馈路径。 输出反相器可以从内部信号或外部引脚选择使能。 逻辑电路可以部署在银行中，每个银行可以接受相同或不同的时钟。 寄存器/锁存器可以通过内部产生的信号或外部引脚预加载。

公开(公告)号：US07573291B1

公开(公告)日：2009-08-11

申请号：US11934711

申请日：2007-11-02

申请人： Om Agrawal ,  Manish Garg ,  Chan-Chi Jason Cheng ,  Satwant Singh ,  Ju Shen

发明人： Om Agrawal ,  Manish Garg ,  Chan-Chi Jason Cheng ,  Satwant Singh ,  Ju Shen

IPC分类号： H03K19/177

CPC分类号： H03K19/17728

摘要： A programmable logic block within a programmable logic device includes at least two interconnected slices, each of the interconnect slices including at least two interconnected lookup tables. Each interconnected lookup table is adapted to receive input signals from a routing structure and to provide a LUT output signal. At least one of the slices includes a register adapted to register the LUT output signal of a lookup table and at least another of the slices includes fewer such registers than lookup tables.

摘要翻译： 可编程逻辑器件内的可编程逻辑块包括至少两个互连的片，每个互连片包括至少两个互连的查找表。 每个互连的查找表适于从路由结构接收输入信号并提供LUT输出信号。 至少一个切片包括适于注册查找表的LUT输出信号的寄存器，并且至少另一个切片包括比查找表少的这样的寄存器。

公开(公告)号：US20050024118A1

公开(公告)日：2005-02-03

申请号：US10629223

申请日：2003-07-29

申请人： Om Agrawal ,  Hans Klein

发明人： Om Agrawal ,  Hans Klein

IPC分类号： G06F1/08 ,  H03L7/18 ,  G06F1/04

CPC分类号： G06F1/08 ,  H03L7/18

摘要： Systems and methods are disclosed to provide clock generation. In accordance with one embodiment, a clock generator chip is provided that is configurable and in-system programmable. The clock generator chip may provide programmable input circuits, programmable output circuits, and permit a JTAG boundary scan.

摘要翻译： 公开了提供时钟生成的系统和方法。 根据一个实施例，提供了一种可配置和可在系统内编程的时钟发生器芯片。 时钟发生器芯片可以提供可编程输入电路，可编程输出电路，并允许JTAG边界扫描。

公开(公告)号：US4933897A

公开(公告)日：1990-06-12

申请号：US356107

申请日：1989-05-24

申请人： Kapil Shankar ,  Om Agrawal

发明人： Kapil Shankar ,  Om Agrawal

IPC分类号： G05B19/045

CPC分类号： G06F9/30061 ,  G05B19/045 ,  G06F9/30036 ,  G05B2219/21115

摘要： A method for designing a control sequencer having a high level counter element and a programmable AND array suitable for control applications. The method utilizes high level constructs bearing a one-to-one relationship to the architecture of the apparatus so that the design of the controller is facilitated resulting in a rapidly-executed program which is easy to comprehend, verify and document. Moore and Mealy state machines are readily implemented by the controller by virtue of its programmable AND array and counter which allow the next-state and output to be based on the contents of the counter as well as any set of input signals. Conditional testing can be made entirely state dependent, partially-state dependent, or state-independent. Multiway branching is also readily implemented since the presence of the programmable AND array allows the user to specify a number of sets of input conditions, so that from a given state, as determined by the counter contents, each set of input condition gives rise to a transition to a specified next state. Instruction decoding for the controller is preformed in the programmable AND array, and thus can be specified by the designer in the high-level software method of the invention. Accordingly, instructions can be stored in the AND array in a logical form directly usable by the hardware. The counter is preferably of the Gray-code type so as to minimize instabilities in the output signals and to permit easy optimization of Boolean expressions involving the state of the device. Dedicated buried registers are provided as are dedicated feedback paths from the outpout registers, dedicated registers and counter to the AND array. Two separate OR arrays are provided, one generating output signals, the other generating control sequencing signals.

摘要翻译： 一种用于设计具有适用于控制应用的高电平计数器元件和可编程AND阵列的控制定序器的方法。 该方法利用与设备架构具有一对一关系的高级结构，从而便于控制器的设计，从而实现易于理解，验证和记录的快速执行的程序。 Moore和Mealy状态机通过其可编程的AND阵列和计数器由控制器容易地实现，其允许下一状态和输出基于计数器的内容以及任何输入信号集合。 条件测试可以完全依赖于状态，部分依赖于状态或与状态无关。 多路分支也容易实现，因为可编程AND阵列的存在允许用户指定多组输入条件，使得从由计数器内容确定的给定状态，每组输入条件产生一个 转换到指定的下一个状态。 控制器的指令解码在可编程AND阵列中执行，因此可以由本发明的高级软件方法中的设计者指定。 因此，指令可以以硬件直接可用的逻辑形式存储在AND阵列中。 该计数器最好是格雷码型，以便最小化输出信号中的不稳定性，并允许容易地优化涉及装置状态的布尔表达式。 专用的寄存器是从输出寄存器，专用寄存器和与数组的计数器的专用反馈路径。 提供两个单独的OR阵列，一个产生输出信号，另一个产生控制定序信号。

公开(公告)号：US08122277B1

公开(公告)日：2012-02-21

申请号：US12578470

申请日：2009-10-13

申请人： Shyam Chandra ,  Om Agrawal ,  Ludmil Nikolov ,  Harald Weller ,  Douglas Morse

发明人： Shyam Chandra ,  Om Agrawal ,  Ludmil Nikolov ,  Harald Weller ,  Douglas Morse

IPC分类号： G06F1/00 ,  G06F1/04 ,  G06F5/06

CPC分类号： G06F1/10

摘要： In one embodiment, a clock distribution chip includes a clock input adapted to receive an input clock signal, clock dividers each adapted to receive a clock signal based on the first input clock signal and to generate a divided clock signal, and programmable clock outputs adapted to provide output clock signals. The clock outputs are configurable to support a number of signaling standards. A programmable switch fabric is coupled between the clock dividers and the clock outputs and is configurable to provide the divided clock signals to the clock outputs.

摘要翻译： 在一个实施例中，时钟分配芯片包括适于接收输入时钟信号的时钟输入，每个时钟分频器适于基于第一输入时钟信号接收时钟信号并产生分频时钟信号，以及可编程时钟输出，其适于 提供输出时钟信号。 时钟输出可配置为支持多种信令标准。 可编程开关结构耦合在时钟分频器和时钟输出之间，可配置为将分频时钟信号提供给时钟输出。

公开(公告)号：US20050024105A1

公开(公告)日：2005-02-03

申请号：US10629221

申请日：2003-07-29

申请人： Om Agrawal ,  Hans Klein ,  Geoffrey Rickard ,  Harald Weller

发明人： Om Agrawal ,  Hans Klein ,  Geoffrey Rickard ,  Harald Weller

IPC分类号： H03L7/089 ,  H03L7/099 ,  H03L7/18 ,  H03L7/06

CPC分类号： H03L7/0891 ,  H03L7/0995 ,  H03L7/0996 ,  H03L7/18

摘要： Systems and methods are disclosed to provide clock generation. In accordance with one embodiment, a clock generator chip is provided that is configurable and in-system programmable and includes a flexible skew control architecture. The clock generator chip may also provide programmable input circuits, programmable output circuits, and permit a JTAG boundary scan.

摘要翻译： 公开了提供时钟生成的系统和方法。 根据一个实施例，提供了一种时钟发生器芯片，其是可配置的并且在系统中可编程并且包括灵活的偏斜控制架构。 时钟发生器芯片还可以提供可编程输入电路，可编程输出电路，并允许JTAG边界扫描。

公开(公告)号：US4931671A

公开(公告)日：1990-06-05

申请号：US178707

申请日：1988-04-07

申请人： Om Agrawal

发明人： Om Agrawal

IPC分类号： H03K19/177

CPC分类号： H03K19/177

摘要： Disclosed is an integrated circuit having multiple programmable arrays providing customizable logic. The integrated circuit has at least a first programmable array receiving a plurality of first inputs and generating a plurality of first outputs as programmed by the user. Also, it includes a second programmable array receiving a plurality of second inputs and generating a plurality of second outputs as programmed by the user. A means for selectiving interconnecting the inputs and outputs from the first and second programmable arrays is provided so that the programmable signals generated can be selectively connected in series, in parallel, or in a combination of series and parallel. Also provided are buried state registers for storing signals as programmed by the user. The stored signals from the buried state registers are likewise selectively interconnected with the input signals and output signals to provide added flexibility and power for the logic designer utilizing the device of the present invention.

摘要翻译： 公开了具有提供可定制逻辑的多个可编程阵列的集成电路。 集成电路至少具有接收多个第一输入的第一可编程阵列，并且产生由用户编程的多个第一输出。 而且，它包括接收多个第二输入并产生由用户编程的多个第二输出的第二可编程阵列。 提供了用于选择互连来自第一和第二可编程阵列的输入和输出的装置，使得所生成的可编程信号可以串联，并联或串联和并联的组合选择性地连接。 还提供了用于存储由用户编程的信号的掩埋状态寄存器。 来自埋置状态寄存器的存储的信号同样与输入信号和输出信号选择性地互连，以为利用本发明的装置的逻辑设计者提供增加的灵活性和功率。