公开(公告)号：US07657773B1

公开(公告)日：2010-02-02

申请号：US11425881

申请日：2006-06-22

申请人： Shyam Chandra ,  Om Agrawal ,  Ludmil Nikolov ,  Harald Weller ,  Douglas Morse

发明人： Shyam Chandra ,  Om Agrawal ,  Ludmil Nikolov ,  Harald Weller ,  Douglas Morse

IPC分类号： G06F1/00 ,  G06F1/04

CPC分类号： G06F1/10

摘要： In one embodiment of the invention, a clock distribution (CD) chip has one or more input pins, input buffer circuitry, clock generation and distribution circuitry, fanout circuitry, one or more output pins, a feedback pin, and feedback buffer circuitry. Based on single-ended or differential input clock signals applied to the input pins, the CD chip can be programmably configured to generate zero, one, or more zero-delay (ZD) output clock signals and zero, one, or more non-zero-delay (NZD) output clock signals for simultaneous presentation at the output pins.

摘要翻译： 在本发明的一个实施例中，时钟分配（CD）芯片具有一个或多个输入引脚，输入缓冲电路，时钟产生和分配电路，扇出电路，一个或多个输出引脚，反馈引脚和反馈缓冲电路。 基于施加到输入引脚的单端或差分输入时钟信号，CD芯片可编程配置为产生零个，一个或多个零延迟（ZD）输出时钟信号，并且零，一个或多个非零 -delay（NZD）输出时钟信号，用于在输出引脚处同时呈现。

公开(公告)号：US08122277B1

公开(公告)日：2012-02-21

申请号：US12578470

申请日：2009-10-13

申请人： Shyam Chandra ,  Om Agrawal ,  Ludmil Nikolov ,  Harald Weller ,  Douglas Morse

发明人： Shyam Chandra ,  Om Agrawal ,  Ludmil Nikolov ,  Harald Weller ,  Douglas Morse

IPC分类号： G06F1/00 ,  G06F1/04 ,  G06F5/06

CPC分类号： G06F1/10

摘要： In one embodiment, a clock distribution chip includes a clock input adapted to receive an input clock signal, clock dividers each adapted to receive a clock signal based on the first input clock signal and to generate a divided clock signal, and programmable clock outputs adapted to provide output clock signals. The clock outputs are configurable to support a number of signaling standards. A programmable switch fabric is coupled between the clock dividers and the clock outputs and is configurable to provide the divided clock signals to the clock outputs.

摘要翻译： 在一个实施例中，时钟分配芯片包括适于接收输入时钟信号的时钟输入，每个时钟分频器适于基于第一输入时钟信号接收时钟信号并产生分频时钟信号，以及可编程时钟输出，其适于 提供输出时钟信号。 时钟输出可配置为支持多种信令标准。 可编程开关结构耦合在时钟分频器和时钟输出之间，可配置为将分频时钟信号提供给时钟输出。

公开(公告)号：US07439783B2

公开(公告)日：2008-10-21

申请号：US11335890

申请日：2006-01-19

申请人： Harald Weller ,  Ludmil Nikolov ,  Ji Zhao

发明人： Harald Weller ,  Ludmil Nikolov ,  Ji Zhao

IPC分类号： H03L7/06

CPC分类号： H03L7/0896 ,  H03L7/0893

摘要： Improved common mode feedback techniques are provided for charge pumps, phase-locked loops (PLLs), and other circuits. For example, in accordance with an embodiment of the present invention, a circuit includes a loop filter having first and second loop filter nodes. An amplifier is provided having first and second differential inputs respectively coupled to the first and second loop filter nodes. A first current source is coupled to the first loop filter node and a second current source is coupled to the second loop filter node. The first and second current sources continuously adjust a common mode voltage of the loop filter nodes.

摘要翻译： 为电荷泵，锁相环（PLL）和其他电路提供了改进的共模反馈技术。 例如，根据本发明的实施例，电路包括具有第一和第二环路滤波器节点的环路滤波器。 提供了具有分别耦合到第一和第二环路滤波器节点的第一和第二差分输入的放大器。 第一电流源耦合到第一环路滤波器节点，而第二电流源耦合到第二环路滤波器节点。 第一和第二电流源连续调节环路滤波器节点的共模电压。

公开(公告)号：US07382169B2

公开(公告)日：2008-06-03

申请号：US11332986

申请日：2006-01-17

申请人： Ludmil Nikolov ,  Harald Weller ,  Michael G. France ,  Ji Zhao

发明人： Ludmil Nikolov ,  Harald Weller ,  Michael G. France ,  Ji Zhao

IPC分类号： H03L7/06

CPC分类号： H03L7/087 ,  H03L7/093

摘要： In accordance with one or more embodiments of the present invention, a system includes a phase-locked loop circuit that receives a reference signal and a feedback signal and provides an output signal. A control circuit also receives the reference signal and the feedback signal and provides a correction current for the phase-locked loop circuit to reduce a phase error of the output signal.

摘要翻译： 根据本发明的一个或多个实施例，系统包括接收参考信号和反馈信号并提供输出信号的锁相环电路。 控制电路还接收参考信号和反馈信号，并为锁相环电路提供校正电流，以减小输出信号的相位误差。

公开(公告)号：US20070164799A1

公开(公告)日：2007-07-19

申请号：US11335890

申请日：2006-01-19

申请人： Harald Weller ,  Ludmil Nikolov ,  Ji Zhao

发明人： Harald Weller ,  Ludmil Nikolov ,  Ji Zhao

IPC分类号： H03L7/06

CPC分类号： H03L7/0896 ,  H03L7/0893

摘要： Improved common mode feedback techniques are provided for charge pumps, phase-locked loops (PLLs), and other circuits. For example, in accordance with an embodiment of the present invention, a circuit includes a loop filter having first and second loop filter nodes. An amplifier is provided having first and second differential inputs respectively coupled to the first and second loop filter nodes. A first current source is coupled to the first loop filter node and a second current source is coupled to the second loop filter node. The first and second current sources are adapted to continuously adjust a common mode voltage of the loop filter nodes.

摘要翻译： 为电荷泵，锁相环（PLL）和其他电路提供了改进的共模反馈技术。 例如，根据本发明的实施例，电路包括具有第一和第二环路滤波器节点的环路滤波器。 提供了具有分别耦合到第一和第二环路滤波器节点的第一和第二差分输入的放大器。 第一电流源耦合到第一环路滤波器节点，而第二电流源耦合到第二环路滤波器节点。 第一和第二电流源适于连续调节环路滤波器节点的共模电压。

公开(公告)号：US20070164798A1

公开(公告)日：2007-07-19

申请号：US11332986

申请日：2006-01-17

申请人： Ludmil Nikolov ,  Harald Weller ,  Michael France ,  Ji Zhao

发明人： Ludmil Nikolov ,  Harald Weller ,  Michael France ,  Ji Zhao

IPC分类号： H03L7/06

CPC分类号： H03L7/087 ,  H03L7/093

摘要： In accordance with one or more embodiments of the present invention, a system includes a phase-locked loop circuit that receives a reference signal and a feedback signal and provides an output signal. A control circuit also receives the reference signal and the feedback signal and provides a correction current for the phase-locked loop circuit to reduce a phase error of the output signal.

摘要翻译： 根据本发明的一个或多个实施例，系统包括接收参考信号和反馈信号并提供输出信号的锁相环电路。 控制电路还接收参考信号和反馈信号，并为锁相环电路提供校正电流，以减小输出信号的相位误差。

公开(公告)号：US20050024105A1

公开(公告)日：2005-02-03

申请号：US10629221

申请日：2003-07-29

申请人： Om Agrawal ,  Hans Klein ,  Geoffrey Rickard ,  Harald Weller

发明人： Om Agrawal ,  Hans Klein ,  Geoffrey Rickard ,  Harald Weller

IPC分类号： H03L7/089 ,  H03L7/099 ,  H03L7/18 ,  H03L7/06

CPC分类号： H03L7/0891 ,  H03L7/0995 ,  H03L7/0996 ,  H03L7/18

摘要： Systems and methods are disclosed to provide clock generation. In accordance with one embodiment, a clock generator chip is provided that is configurable and in-system programmable and includes a flexible skew control architecture. The clock generator chip may also provide programmable input circuits, programmable output circuits, and permit a JTAG boundary scan.

摘要翻译： 公开了提供时钟生成的系统和方法。 根据一个实施例，提供了一种时钟发生器芯片，其是可配置的并且在系统中可编程并且包括灵活的偏斜控制架构。 时钟发生器芯片还可以提供可编程输入电路，可编程输出电路，并允许JTAG边界扫描。

公开(公告)号：US08112656B1

公开(公告)日：2012-02-07

申请号：US12578492

申请日：2009-10-13

申请人： Shyam Chandra ,  Om Agrawal ,  Ludmil Nikolov ,  Harald Weller ,  Douglas Morse

发明人： Shyam Chandra ,  Om Agrawal ,  Ludmil Nikolov ,  Harald Weller ,  Douglas Morse

IPC分类号： G06F1/00 ,  G06F1/04 ,  G06F1/12 ,  G06F5/06

CPC分类号： G06F1/10

摘要： In one embodiment, a clock distribution chip includes a first clock input adapted to receive a first single-ended input clock signal, a second clock input adapted to receive a second single-ended input clock signal, and input buffer circuitry coupled to the first and second clock inputs. The input buffer circuitry is adapted to select an input clock signal among the first single-ended input clock signal, the second single-ended input clock signal, and a differential input clock signal derived from the first and second single-ended input clock signals. A phase-locked loop (PLL) is adapted to receive an input clock signal selected by the input buffer circuitry and to generate a PLL clock signal based on the selected input clock signal. A clock output provides an output clock signal based on the PLL clock signal.

摘要翻译： 在一个实施例中，时钟分配芯片包括适于接收第一单端输入时钟信号的第一时钟输入，适于接收第二单端输入时钟信号的第二时钟输入以及耦合到第一和第 第二个时钟输入。 输入缓冲器电路适于在第一单端输入时钟信号，第二单端输入时钟信号和从第一和第二单端输入时钟信号导出的差分输入时钟信号之间选择输入时钟信号。 锁相环（PLL）适于接收由输入缓冲器电路选择的输入时钟信号，并且基于所选择的输入时钟信号产生PLL时钟信号。 时钟输出提供基于PLL时钟信号的输出时钟信号。