公开(公告)号：US20070164798A1

公开(公告)日：2007-07-19

申请号：US11332986

申请日：2006-01-17

申请人： Ludmil Nikolov ,  Harald Weller ,  Michael France ,  Ji Zhao

发明人： Ludmil Nikolov ,  Harald Weller ,  Michael France ,  Ji Zhao

IPC分类号： H03L7/06

CPC分类号： H03L7/087 ,  H03L7/093

摘要： In accordance with one or more embodiments of the present invention, a system includes a phase-locked loop circuit that receives a reference signal and a feedback signal and provides an output signal. A control circuit also receives the reference signal and the feedback signal and provides a correction current for the phase-locked loop circuit to reduce a phase error of the output signal.

摘要翻译： 根据本发明的一个或多个实施例，系统包括接收参考信号和反馈信号并提供输出信号的锁相环电路。 控制电路还接收参考信号和反馈信号，并为锁相环电路提供校正电流，以减小输出信号的相位误差。

公开(公告)号：US07439783B2

公开(公告)日：2008-10-21

申请号：US11335890

申请日：2006-01-19

申请人： Harald Weller ,  Ludmil Nikolov ,  Ji Zhao

发明人： Harald Weller ,  Ludmil Nikolov ,  Ji Zhao

IPC分类号： H03L7/06

CPC分类号： H03L7/0896 ,  H03L7/0893

摘要： Improved common mode feedback techniques are provided for charge pumps, phase-locked loops (PLLs), and other circuits. For example, in accordance with an embodiment of the present invention, a circuit includes a loop filter having first and second loop filter nodes. An amplifier is provided having first and second differential inputs respectively coupled to the first and second loop filter nodes. A first current source is coupled to the first loop filter node and a second current source is coupled to the second loop filter node. The first and second current sources continuously adjust a common mode voltage of the loop filter nodes.

摘要翻译： 为电荷泵，锁相环（PLL）和其他电路提供了改进的共模反馈技术。 例如，根据本发明的实施例，电路包括具有第一和第二环路滤波器节点的环路滤波器。 提供了具有分别耦合到第一和第二环路滤波器节点的第一和第二差分输入的放大器。 第一电流源耦合到第一环路滤波器节点，而第二电流源耦合到第二环路滤波器节点。 第一和第二电流源连续调节环路滤波器节点的共模电压。

公开(公告)号：US07382169B2

公开(公告)日：2008-06-03

申请号：US11332986

申请日：2006-01-17

申请人： Ludmil Nikolov ,  Harald Weller ,  Michael G. France ,  Ji Zhao

发明人： Ludmil Nikolov ,  Harald Weller ,  Michael G. France ,  Ji Zhao

IPC分类号： H03L7/06

CPC分类号： H03L7/087 ,  H03L7/093

摘要： In accordance with one or more embodiments of the present invention, a system includes a phase-locked loop circuit that receives a reference signal and a feedback signal and provides an output signal. A control circuit also receives the reference signal and the feedback signal and provides a correction current for the phase-locked loop circuit to reduce a phase error of the output signal.

摘要翻译： 根据本发明的一个或多个实施例，系统包括接收参考信号和反馈信号并提供输出信号的锁相环电路。 控制电路还接收参考信号和反馈信号，并为锁相环电路提供校正电流，以减小输出信号的相位误差。

公开(公告)号：US20070164799A1

公开(公告)日：2007-07-19

申请号：US11335890

申请日：2006-01-19

申请人： Harald Weller ,  Ludmil Nikolov ,  Ji Zhao

发明人： Harald Weller ,  Ludmil Nikolov ,  Ji Zhao

IPC分类号： H03L7/06

CPC分类号： H03L7/0896 ,  H03L7/0893

摘要： Improved common mode feedback techniques are provided for charge pumps, phase-locked loops (PLLs), and other circuits. For example, in accordance with an embodiment of the present invention, a circuit includes a loop filter having first and second loop filter nodes. An amplifier is provided having first and second differential inputs respectively coupled to the first and second loop filter nodes. A first current source is coupled to the first loop filter node and a second current source is coupled to the second loop filter node. The first and second current sources are adapted to continuously adjust a common mode voltage of the loop filter nodes.

摘要翻译： 为电荷泵，锁相环（PLL）和其他电路提供了改进的共模反馈技术。 例如，根据本发明的实施例，电路包括具有第一和第二环路滤波器节点的环路滤波器。 提供了具有分别耦合到第一和第二环路滤波器节点的第一和第二差分输入的放大器。 第一电流源耦合到第一环路滤波器节点，而第二电流源耦合到第二环路滤波器节点。 第一和第二电流源适于连续调节环路滤波器节点的共模电压。

公开(公告)号：US07657773B1

公开(公告)日：2010-02-02

申请号：US11425881

申请日：2006-06-22

申请人： Shyam Chandra ,  Om Agrawal ,  Ludmil Nikolov ,  Harald Weller ,  Douglas Morse

发明人： Shyam Chandra ,  Om Agrawal ,  Ludmil Nikolov ,  Harald Weller ,  Douglas Morse

IPC分类号： G06F1/00 ,  G06F1/04

CPC分类号： G06F1/10

摘要： In one embodiment of the invention, a clock distribution (CD) chip has one or more input pins, input buffer circuitry, clock generation and distribution circuitry, fanout circuitry, one or more output pins, a feedback pin, and feedback buffer circuitry. Based on single-ended or differential input clock signals applied to the input pins, the CD chip can be programmably configured to generate zero, one, or more zero-delay (ZD) output clock signals and zero, one, or more non-zero-delay (NZD) output clock signals for simultaneous presentation at the output pins.

摘要翻译： 在本发明的一个实施例中，时钟分配（CD）芯片具有一个或多个输入引脚，输入缓冲电路，时钟产生和分配电路，扇出电路，一个或多个输出引脚，反馈引脚和反馈缓冲电路。 基于施加到输入引脚的单端或差分输入时钟信号，CD芯片可编程配置为产生零个，一个或多个零延迟（ZD）输出时钟信号，并且零，一个或多个非零 -delay（NZD）输出时钟信号，用于在输出引脚处同时呈现。

公开(公告)号：US08112656B1

公开(公告)日：2012-02-07

申请号：US12578492

申请日：2009-10-13

申请人： Shyam Chandra ,  Om Agrawal ,  Ludmil Nikolov ,  Harald Weller ,  Douglas Morse

发明人： Shyam Chandra ,  Om Agrawal ,  Ludmil Nikolov ,  Harald Weller ,  Douglas Morse

IPC分类号： G06F1/00 ,  G06F1/04 ,  G06F1/12 ,  G06F5/06

CPC分类号： G06F1/10

摘要： In one embodiment, a clock distribution chip includes a first clock input adapted to receive a first single-ended input clock signal, a second clock input adapted to receive a second single-ended input clock signal, and input buffer circuitry coupled to the first and second clock inputs. The input buffer circuitry is adapted to select an input clock signal among the first single-ended input clock signal, the second single-ended input clock signal, and a differential input clock signal derived from the first and second single-ended input clock signals. A phase-locked loop (PLL) is adapted to receive an input clock signal selected by the input buffer circuitry and to generate a PLL clock signal based on the selected input clock signal. A clock output provides an output clock signal based on the PLL clock signal.

摘要翻译： 在一个实施例中，时钟分配芯片包括适于接收第一单端输入时钟信号的第一时钟输入，适于接收第二单端输入时钟信号的第二时钟输入以及耦合到第一和第 第二个时钟输入。 输入缓冲器电路适于在第一单端输入时钟信号，第二单端输入时钟信号和从第一和第二单端输入时钟信号导出的差分输入时钟信号之间选择输入时钟信号。 锁相环（PLL）适于接收由输入缓冲器电路选择的输入时钟信号，并且基于所选择的输入时钟信号产生PLL时钟信号。 时钟输出提供基于PLL时钟信号的输出时钟信号。

公开(公告)号：US08122277B1

公开(公告)日：2012-02-21

申请号：US12578470

申请日：2009-10-13

申请人： Shyam Chandra ,  Om Agrawal ,  Ludmil Nikolov ,  Harald Weller ,  Douglas Morse

发明人： Shyam Chandra ,  Om Agrawal ,  Ludmil Nikolov ,  Harald Weller ,  Douglas Morse

IPC分类号： G06F1/00 ,  G06F1/04 ,  G06F5/06

CPC分类号： G06F1/10

摘要： In one embodiment, a clock distribution chip includes a clock input adapted to receive an input clock signal, clock dividers each adapted to receive a clock signal based on the first input clock signal and to generate a divided clock signal, and programmable clock outputs adapted to provide output clock signals. The clock outputs are configurable to support a number of signaling standards. A programmable switch fabric is coupled between the clock dividers and the clock outputs and is configurable to provide the divided clock signals to the clock outputs.

摘要翻译： 在一个实施例中，时钟分配芯片包括适于接收输入时钟信号的时钟输入，每个时钟分频器适于基于第一输入时钟信号接收时钟信号并产生分频时钟信号，以及可编程时钟输出，其适于 提供输出时钟信号。 时钟输出可配置为支持多种信令标准。 可编程开关结构耦合在时钟分频器和时钟输出之间，可配置为将分频时钟信号提供给时钟输出。

公开(公告)号：US20070201543A1

公开(公告)日：2007-08-30

申请号：US11362289

申请日：2006-02-24

申请人： Ludmil Nikolov ,  Michael France

发明人： Ludmil Nikolov ,  Michael France

IPC分类号： H04B3/46

CPC分类号： H04B3/462 ,  G01R31/31709 ,  H03L7/06

摘要： In one embodiment, a method is provided for measuring a dynamic phase offset between a PLL's input clock and the PLL's feedback input clock, wherein the input clock is spread spectrum modulated in a spread spectrum mode and is not modulated in a static mode. The method includes: in the spread spectrum mode, measuring phase jitter between the input clock and the feedback input clock to form a spread spectrum phase jitter measurement; in the static mode, measuring phase jitter between the input clock and the feedback input clock to form a static phase jitter measurement; and comparing the spread spectrum phase jitter measurement to the static phase jitter measurement to determine the dynamic phase offset.

摘要翻译： 在一个实施例中，提供了一种用于测量PLL的输入时钟和PLL的反馈输入时钟之间的动态相位偏移的方法，其中输入时钟以扩展频谱模式被扩频调制并且不以静态模式调制。 该方法包括：在扩频模式下，测量输入时钟和反馈输入时钟之间的相位抖动，形成扩频相位抖动测量; 在静态模式下，测量输入时钟和反馈输入时钟之间的相位抖动，形成静态相位抖动测量; 并将扩频相位抖动测量与静态相位抖动测量进行比较，以确定动态相位偏移。

公开(公告)号：US20120261994A1

公开(公告)日：2012-10-18

申请号：US13066611

申请日：2011-04-19

申请人： Ludmil Nikolov ,  Carlos Calisto

发明人： Ludmil Nikolov ,  Carlos Calisto

IPC分类号： H02J9/06

CPC分类号： H02J9/061 ,  G06F1/30 ,  H02J9/04 ,  H02J9/06 ,  Y10T307/344 ,  Y10T307/615 ,  Y10T307/625

摘要： Circuits and methods providing a electronic power supply applicable to any dual supply rail systems, which require a smooth and uninterrupted output supply and a replica power path and autonomous mode of operation from the system power supply are disclosed. In a preferred embodiment of the invention the power supply is applied to a real time clock. An Innovative Replica Power Path concept and circuit implementation ensures the smooth and uninterrupted transfer of power from one input source to the other. The circuit features a Latched Supply Comparator that guarantees the commutation to the Replica Power Path only happens after the voltage is settled. Zero power consumption from the back-up energy source is achieved in the presence of an alternative higher voltage source. The generated RTC supply voltage does not suffer from abrupt changes when the voltage level of the main system power source (battery or charger) is connected or disconnected. The invention allows for maximum utilization of the energy left in the main battery, thus extending the life of the lower capacity backup battery/super-cap.

摘要翻译： 公开了提供适用于需要平滑且不间断的输出电源和复制电源路径以及从系统电源的自主操作模式的任何双电源轨系统的电子电源的电路和方法。 在本发明的优选实施例中，将电源施加到实时时钟。 创新的复制权力路径概念和电路实现确保了从一个输入源到另一个输入源的平滑和不间断的电力传输。 该电路具有锁存电源比较器，保证只有在电压稳定后，才能对复制电源通道进行换向。 在替代的更高电压源的存在下实现来自备用能源的零功率消耗。 当主系统电源（电池或充电器）的电压电平连接或断开时，产生的RTC电源电压不会发生突然变化。 本发明允许最大限度地利用主电池中留下的能量，从而延长了较低容量的备用电池/超级盖的寿命。

公开(公告)号：US20120229117A1

公开(公告)日：2012-09-13

申请号：US12932995

申请日：2011-03-11

申请人： Ludmil Nikolov ,  Carlos Calisto

发明人： Ludmil Nikolov ,  Carlos Calisto

IPC分类号： G05F3/16

CPC分类号： G05F3/242

摘要： A self-biased reference circuit device (100) includes a first cascode current mirror (116), a second cascode current mirror (118), and a startup circuit (108). The first cascode current mirror (116) is capable to generate a first bias voltage (136) and a second bias voltage (140) in response to a first current and to generate a second current in response to the first and second bias voltages. The second cascode current mirror (118) is capable to generate a third bias voltage (164) in response to the second current, to generate a fourth bias voltage (168) in response to a third current, and to generate the first current in response to the third and fourth bias voltages. The startup circuit includes a first switch (188) and a second switch (196). The first switch (188) is capable to connect the first bias voltage (136) and fourth bias voltage (168) during startup. The second switch (196) is capable to connect the third bias voltage (164) and an inner drain-source connection (130) in the output stage of the first cascode current mirror (116) during startup.

摘要翻译： 自偏置参考电路装置（100）包括第一共源共栅电流镜（116），第二共源共栅电流镜（118）和启动电路（108）。 第一级联电流镜（116）能够响应于第一电流产生第一偏置电压（136）和第二偏置电压（140），并且响应于第一和第二偏置电压产生第二电流。 第二共源共栅电流镜（118）能够响应于第二电流产生第三偏置电压（164），以响应于第三电流产生第四偏置电压（168），并且响应于产生第一电流 到第三和第四偏置电压。 启动电路包括第一开关（188）和第二开关（196）。 第一开关（188）能够在启动期间连接第一偏置电压（136）和第四偏置电压（168）。 第二开关（196）能够在启动期间连接第一共源共栅电流镜（116）的输出级中的第三偏置电压（164）和内部漏极 - 源极连接（130）。