公开(公告)号：US20100261324A1

公开(公告)日：2010-10-14

申请号：US12802894

申请日：2010-06-16

申请人： Tomoko Ogura ,  Seiki Ogura ,  Nori Ogura

发明人： Tomoko Ogura ,  Seiki Ogura ,  Nori Ogura

IPC分类号： H01L21/336

CPC分类号： G11C16/0466 ,  G11C16/0475 ,  H01L27/115

摘要： A nonvolatile trap charge storage cell selects a logic interconnect transistor uses in programmable logic applications, such as FPGA. The nonvolatile trap charge element is an insulator located under a control gate and above an oxide on the surface of a semiconductor substrate. The preferred embodiment is an integrated device comprising a word gate portion sandwiched between two nonvolatile trap charge storage portions, wherein the integrated device is connected between a high bias, a low bias and an output. The output is formed by a diffusion connecting to the channel directly under the word gate portion. The program state of the two storage portions determines whether the high bias or the low bias is coupled to a logic interconnect transistor connected to the output diffusion.

摘要翻译： 非易失性陷阱电荷存储单元选择在可编程逻辑应用中使用的逻辑互连晶体管，例如FPGA。 非挥发性捕获电荷元件是位于控制栅极下方并位于半导体衬底表面上的氧化物之上的绝缘体。 优选实施例是集成器件，其包括夹在两个非易失性陷阱电荷存储部分之间的字门部分，其中该集成器件连接在高偏压，低偏压和输出之间。 输出由连接到字栅极下方的通道的扩散形成。 两个存储部分的编程状态确定高偏压或低偏压是否耦合到连接到输出扩散的逻辑互连晶体管。

公开(公告)号：US20100259985A1

公开(公告)日：2010-10-14

申请号：US12802895

申请日：2010-06-16

申请人： Tomoko Ogura ,  Seiki Ogura ,  Nori Ogura

发明人： Tomoko Ogura ,  Seiki Ogura ,  Nori Ogura

IPC分类号： G11C16/04

CPC分类号： G11C16/0466 ,  G11C16/0475 ,  H01L27/115

摘要： A nonvolatile trap charge storage cell selects a logic interconnect transistor uses in programmable logic applications, such as FPGA. The nonvolatile trap charge element is an insulator located under a control gate and above an oxide on the surface of a semiconductor substrate. The preferred embodiment is an integrated device comprising a word gate portion sandwiched between two nonvolatile trap charge storage portions, wherein the integrated device is connected between a high bias, a low bias and an output. The output is formed by a diffusion connecting to the channel directly under the word gate portion. The program state of the two storage portions determines whether the high bias or the low bias is coupled to a logic interconnect transistor connected to the output diffusion.

公开(公告)号：US20080101117A1

公开(公告)日：2008-05-01

申请号：US11982172

申请日：2007-11-01

申请人： Tomoko Ogura ,  Seiki Ogura ,  Nori Ogura

发明人： Tomoko Ogura ,  Seiki Ogura ,  Nori Ogura

IPC分类号： G11C16/04 ,  H01L21/336

CPC分类号： G11C16/0466 ,  G11C16/0475 ,  H01L27/115

摘要： A nonvolatile trap charge storage cell selects a logic interconnect transistor uses in programmable logic applications, such as FPGA. The nonvolatile trap charge element is an insulator located under a control gate and above an oxide on the surface of a semiconductor substrate. The preferred embodiment is an integrated device comprising a word gate portion sandwiched between two nonvolatile trap charge storage portions, wherein the integrated device is connected between a high bias, a low bias and an output. The output is formed by a diffusion connecting to the channel directly under the word gate portion. The program state of the two storage portions determines whether the high bias or the low bias is coupled to a logic interconnect transistor connected to the output diffusion.

摘要翻译： 非易失性陷阱电荷存储单元选择在可编程逻辑应用中使用的逻辑互连晶体管，例如FPGA。 非挥发性捕获电荷元件是位于控制栅极下方并位于半导体衬底表面上的氧化物之上的绝缘体。 优选实施例是集成器件，其包括夹在两个非易失性陷阱电荷存储部分之间的字门部分，其中该集成器件连接在高偏压，低偏压和输出之间。 输出由连接到字栅极下方的通道的扩散形成。 两个存储部分的编程状态确定高偏压或低偏压是否耦合到连接到输出扩散的逻辑互连晶体管。

公开(公告)号：US06636439B1

公开(公告)日：2003-10-21

申请号：US10371840

申请日：2003-02-20

申请人： Seiki Ogura ,  Tomoko Ogura ,  Nori Ogura

发明人： Seiki Ogura ,  Tomoko Ogura ,  Nori Ogura

IPC分类号： G11C1604

CPC分类号： G11C16/3459 ,  G11C16/0475 ,  G11C16/12 ,  G11C16/3454

摘要： In the present invention a new method for program and program verify is described. The threshold voltage of the memory cell is shifted up and then measured with minimal charging and discharging of the bit lines and control gate lines. Bit line to control gate line capacitance is also used to reduce the number of voltage references needed. Program current is reduced by use of a load device coupled to the source diffusion. The result is increased program bandwidth with lower high voltage charge pump current consumption.

公开(公告)号：US06549463B2

公开(公告)日：2003-04-15

申请号：US10016916

申请日：2001-12-14

申请人： Seiki Ogura ,  Tomoko Ogura ,  Nori Ogura

发明人： Seiki Ogura ,  Tomoko Ogura ,  Nori Ogura

IPC分类号： G11C1604

CPC分类号： G11C16/3459 ,  G11C16/0475 ,  G11C16/12 ,  G11C16/3454

摘要： In the present invention a new method for program and program verify is described. The threshold voltage of the memory cell is shifted up and then measured with minimal charging and discharging of the bit lines and control gate lines. Bit line to control gate line capacitance is also used to reduce the number of voltage references needed. Program current is reduced by use of a load device coupled to the source diffusion. The result is increased program bandwidth with lower high voltage charge pump current consumption.

公开(公告)号：US20130094299A1

公开(公告)日：2013-04-18

申请号：US13692503

申请日：2012-12-03

申请人： Nori Ogura ,  Tomoko Ogura ,  Seiki Ogura

发明人： Nori Ogura ,  Tomoko Ogura ,  Seiki Ogura

IPC分类号： G11C16/06 ,  G11C16/04

CPC分类号： G11C16/06 ,  G11C7/04 ,  G11C7/06 ,  G11C7/10 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/04 ,  G11C16/0466 ,  G11C16/10 ,  G11C2211/5647

摘要： Methods of complementary pairing of memory cells are described. These methods include two physical memory cells in a complementary pair, a complementary pair of reference cells for each erase block, and a physical complementary pair storing multiple data bits.

摘要翻译： 描述了存储器单元的互补配对的方法。 这些方法包括互补对中的两个物理存储器单元，每个擦除块的互补对参考单元，以及存储多个数据位的物理互补对。

公开(公告)号：US08325542B2

公开(公告)日：2012-12-04

申请号：US12583743

申请日：2009-08-25

申请人： Nori Ogura ,  Tomoko Ogura ,  Seiki Ogura

发明人： Nori Ogura ,  Tomoko Ogura ,  Seiki Ogura

IPC分类号： G11C7/00

CPC分类号： G11C16/06 ,  G11C7/04 ,  G11C7/06 ,  G11C7/10 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/04 ,  G11C16/0466 ,  G11C16/10 ,  G11C2211/5647

摘要： Methods of complementary pairing of memory cells are described. These methods include two physical memory cells in a complementary pair, a complementary pair of reference cells for each erase block, and a physical complementary pair storing multiple data bits.

摘要翻译： 描述了存储器单元的互补配对的方法。 这些方法包括互补对中的两个物理存储器单元，每个擦除块的互补对参考单元，以及存储多个数据位的物理互补对。

公开(公告)号：US08174885B2

公开(公告)日：2012-05-08

申请号：US13068066

申请日：2011-05-02

申请人： Tomoko Ogura ,  Nori Ogura ,  Seiki Ogura ,  Tomoya Saito ,  Yoshitaka Baba

发明人： Tomoko Ogura ,  Nori Ogura ,  Seiki Ogura ,  Tomoya Saito ,  Yoshitaka Baba

IPC分类号： G11C11/34

CPC分类号： G11C16/0475

摘要： The present invention provides a novel read method of twin MONOS metal bit or diffusion bit structure for high-speed application. In a first embodiment of the present invention, the alternative control gates are set at the same voltage. In a second embodiment of the present invention, all the control gates are set at the operational voltage from the beginning. In both embodiments, the bit line and word gate are used to address the selected memory cell.teh

摘要翻译： 本发明提供了一种用于高速应用的双MONOS金属钻头或扩散钻头结构的新型读取方法。 在本发明的第一实施例中，替代控制栅极被设置在相同的电压。 在本发明的第二实施例中，所有的控制栅极都从一开始就被设定为工作电压。 在两个实施例中，位线和字门用于对选定的存储单元进行寻址

公开(公告)号：US08089809B2

公开(公告)日：2012-01-03

申请号：US12802888

申请日：2010-06-16

申请人： Tomoko Ogura ,  Seiki Ogura ,  Nori Ogura

发明人： Tomoko Ogura ,  Seiki Ogura ,  Nori Ogura

IPC分类号： G11C16/04

CPC分类号： G11C16/0466 ,  G11C16/0475 ,  H01L27/115

摘要： A nonvolatile trap charge storage cell selects a logic interconnect transistor uses in programmable logic applications, such as FPGA. The nonvolatile trap charge element is an insulator located under a control gate and above an oxide on the surface of a semiconductor substrate. The preferred embodiment is an integrated device comprising a word gate portion sandwiched between two nonvolatile trap charge storage portions, wherein the integrated device is connected between a high bias, a low bias and an output. The output is formed by a diffusion connecting to the channel directly under the word gate portion. The program state of the two storage portions determines whether the high bias or the low bias is coupled to a logic interconnect transistor connected to the output diffusion.

摘要翻译： 非易失性陷阱电荷存储单元选择在可编程逻辑应用中使用的逻辑互连晶体管，例如FPGA。 非挥发性捕获电荷元件是位于控制栅极下方并位于半导体衬底表面上的氧化物之上的绝缘体。 优选实施例是集成器件，其包括夹在两个非易失性陷阱电荷存储部分之间的字门部分，其中该集成器件连接在高偏压，低偏压和输出之间。 输出由连接到字栅极下方的通道的扩散形成。 两个存储部分的编程状态确定高偏压或低偏压是否耦合到连接到输出扩散的逻辑互连晶体管。

公开(公告)号：US07447077B2

公开(公告)日：2008-11-04

申请号：US11500115

申请日：2006-08-07

申请人： Tomoko Ogura ,  Nori Ogura ,  Seiki Ogura ,  Yoshitaka Baba

发明人： Tomoko Ogura ,  Nori Ogura ,  Seiki Ogura ,  Yoshitaka Baba

IPC分类号： G11C11/34

CPC分类号： G11C7/14 ,  G11C16/0475 ,  G11C16/28 ,  G11C16/3445 ,  G11C16/3454 ,  G11C16/3459

摘要： A reference circuit is described for creating a reference signal using a twin MONOS memory cell. A first portion of the twin MONOS memory cell connects to a charged and floating bit line a current source formed in a second portion of the twin MONOS cell that discharges the charged bit line to form a reference signal for a sense amplifier. The sense amplifier compares the reference signal to a signal from a selected memory cell upon which memory operations are being performed comprising read, erase verify and program verify.

摘要翻译： 描述了使用双MONOS存储单元创建参考信号的参考电路。 双MONOS存储器单元的第一部分连接到充电和浮置位线，形成在双MONOS单元的第二部分中的电流源，其对充电的位线进行放电以形成用于读出放大器的参考信号。 读出放大器将参考信号与来自执行存储器操作的所选存储器单元的信号进行比较，包括读取，擦除验证和程序验证。