发明授权
- 专利标题: Referencing scheme for trap memory
- 专利标题(中): 陷阱内存引用方案
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申请号: US11500115申请日: 2006-08-07
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公开(公告)号: US07447077B2公开(公告)日: 2008-11-04
- 发明人: Tomoko Ogura , Nori Ogura , Seiki Ogura , Yoshitaka Baba
- 申请人: Tomoko Ogura , Nori Ogura , Seiki Ogura , Yoshitaka Baba
- 申请人地址: US OR Hillsboro
- 专利权人: Halo LSI, Inc.
- 当前专利权人: Halo LSI, Inc.
- 当前专利权人地址: US OR Hillsboro
- 代理机构: Saile Ackerman LLC
- 代理商 Stephen B. Ackerman
- 主分类号: G11C11/34
- IPC分类号: G11C11/34
摘要:
A reference circuit is described for creating a reference signal using a twin MONOS memory cell. A first portion of the twin MONOS memory cell connects to a charged and floating bit line a current source formed in a second portion of the twin MONOS cell that discharges the charged bit line to form a reference signal for a sense amplifier. The sense amplifier compares the reference signal to a signal from a selected memory cell upon which memory operations are being performed comprising read, erase verify and program verify.
公开/授权文献
- US20070030745A1 Referencing scheme for trap memory 公开/授权日:2007-02-08
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