公开(公告)号：US20100261324A1

公开(公告)日：2010-10-14

申请号：US12802894

申请日：2010-06-16

申请人： Tomoko Ogura ,  Seiki Ogura ,  Nori Ogura

发明人： Tomoko Ogura ,  Seiki Ogura ,  Nori Ogura

IPC分类号： H01L21/336

CPC分类号： G11C16/0466 ,  G11C16/0475 ,  H01L27/115

摘要： A nonvolatile trap charge storage cell selects a logic interconnect transistor uses in programmable logic applications, such as FPGA. The nonvolatile trap charge element is an insulator located under a control gate and above an oxide on the surface of a semiconductor substrate. The preferred embodiment is an integrated device comprising a word gate portion sandwiched between two nonvolatile trap charge storage portions, wherein the integrated device is connected between a high bias, a low bias and an output. The output is formed by a diffusion connecting to the channel directly under the word gate portion. The program state of the two storage portions determines whether the high bias or the low bias is coupled to a logic interconnect transistor connected to the output diffusion.

摘要翻译： 非易失性陷阱电荷存储单元选择在可编程逻辑应用中使用的逻辑互连晶体管，例如FPGA。 非挥发性捕获电荷元件是位于控制栅极下方并位于半导体衬底表面上的氧化物之上的绝缘体。 优选实施例是集成器件，其包括夹在两个非易失性陷阱电荷存储部分之间的字门部分，其中该集成器件连接在高偏压，低偏压和输出之间。 输出由连接到字栅极下方的通道的扩散形成。 两个存储部分的编程状态确定高偏压或低偏压是否耦合到连接到输出扩散的逻辑互连晶体管。

公开(公告)号：US20100259985A1

公开(公告)日：2010-10-14

申请号：US12802895

申请日：2010-06-16

申请人： Tomoko Ogura ,  Seiki Ogura ,  Nori Ogura

发明人： Tomoko Ogura ,  Seiki Ogura ,  Nori Ogura

IPC分类号： G11C16/04

CPC分类号： G11C16/0466 ,  G11C16/0475 ,  H01L27/115

摘要： A nonvolatile trap charge storage cell selects a logic interconnect transistor uses in programmable logic applications, such as FPGA. The nonvolatile trap charge element is an insulator located under a control gate and above an oxide on the surface of a semiconductor substrate. The preferred embodiment is an integrated device comprising a word gate portion sandwiched between two nonvolatile trap charge storage portions, wherein the integrated device is connected between a high bias, a low bias and an output. The output is formed by a diffusion connecting to the channel directly under the word gate portion. The program state of the two storage portions determines whether the high bias or the low bias is coupled to a logic interconnect transistor connected to the output diffusion.

公开(公告)号：US20080101117A1

公开(公告)日：2008-05-01

申请号：US11982172

申请日：2007-11-01

申请人： Tomoko Ogura ,  Seiki Ogura ,  Nori Ogura

发明人： Tomoko Ogura ,  Seiki Ogura ,  Nori Ogura

IPC分类号： G11C16/04 ,  H01L21/336

CPC分类号： G11C16/0466 ,  G11C16/0475 ,  H01L27/115

摘要： A nonvolatile trap charge storage cell selects a logic interconnect transistor uses in programmable logic applications, such as FPGA. The nonvolatile trap charge element is an insulator located under a control gate and above an oxide on the surface of a semiconductor substrate. The preferred embodiment is an integrated device comprising a word gate portion sandwiched between two nonvolatile trap charge storage portions, wherein the integrated device is connected between a high bias, a low bias and an output. The output is formed by a diffusion connecting to the channel directly under the word gate portion. The program state of the two storage portions determines whether the high bias or the low bias is coupled to a logic interconnect transistor connected to the output diffusion.

摘要翻译： 非易失性陷阱电荷存储单元选择在可编程逻辑应用中使用的逻辑互连晶体管，例如FPGA。 非挥发性捕获电荷元件是位于控制栅极下方并位于半导体衬底表面上的氧化物之上的绝缘体。 优选实施例是集成器件，其包括夹在两个非易失性陷阱电荷存储部分之间的字门部分，其中该集成器件连接在高偏压，低偏压和输出之间。 输出由连接到字栅极下方的通道的扩散形成。 两个存储部分的编程状态确定高偏压或低偏压是否耦合到连接到输出扩散的逻辑互连晶体管。

公开(公告)号：US07352033B2

公开(公告)日：2008-04-01

申请号：US11215528

申请日：2005-08-30

申请人： Kimihiro Satoh ,  Tomoko Ogura ,  Ki-Tae Park ,  Nori Ogura ,  Yoshitaka Baba

发明人： Kimihiro Satoh ,  Tomoko Ogura ,  Ki-Tae Park ,  Nori Ogura ,  Yoshitaka Baba

IPC分类号： H01L29/772

CPC分类号： G11C16/08 ,  G11C16/0466 ,  G11C16/16 ,  H01L29/792

摘要： The invention provides a metal bit structure of Twin MONOS memory cell with large channel width and its operational method for high-speed applications using a metal bit array.

摘要翻译： 本发明提供了具有大通道宽度的双MONOS存储单元的金属钻头结构及其使用金属钻头阵列的高速应用的操作方法。

公开(公告)号：US07149126B2

公开(公告)日：2006-12-12

申请号：US10756568

申请日：2004-01-13

申请人： Seiki Ogura ,  Yutaka Hayashi ,  Tomoko Ogura

发明人： Seiki Ogura ,  Yutaka Hayashi ,  Tomoko Ogura

IPC分类号： G11C16/04

CPC分类号： H01L27/11568 ,  G11C11/5671 ,  G11C16/0475 ,  H01L27/115

摘要： A fast low voltage ballistic program, ultra-short channel, ultra-high density, dual-bit multi-level flash memory is described. The structure and operation of this invention is enabled by a twin MONOS cell structure having an ultra-short control gate channel of less than 40 nm, with ballistic injection which provides high electron injection efficiency and very fast program at low program voltages of 3˜5V. The ballistic MONOS memory cell is arranged in the following array: each memory cell contains two nitride regions for one word gate, and ½ a source diffusion and ½ a bit diffusion. Control gates can be defined separately or shared together over the same diffusion. Diffusions are shared between cells and run in parallel to the side wall control gates, and perpendicular to the word line.

摘要翻译： 描述了一种快速低电压弹道程序，超短通道，超高密度双位多级闪存。 本发明的结构和操作通过具有小于40nm的超短控制栅极通道的双重MONOS单元结构实现，具有提供高电子注入效率的弹道注入和在3〜5V的低编程电压下非常快速的程序 。 弹道MONOS存储单元被布置在以下阵列中：每个存储单元包含用于一个字门的两个氮化物区域，以及1/2扩散源和1/2位扩散。 控制门可以单独定义，也可以通过相同的扩散共享。 扩散在单元之间共享并且平行于侧壁控制栅极并垂直于字线。

公开(公告)号：US06636439B1

公开(公告)日：2003-10-21

申请号：US10371840

申请日：2003-02-20

申请人： Seiki Ogura ,  Tomoko Ogura ,  Nori Ogura

发明人： Seiki Ogura ,  Tomoko Ogura ,  Nori Ogura

IPC分类号： G11C1604

CPC分类号： G11C16/3459 ,  G11C16/0475 ,  G11C16/12 ,  G11C16/3454

摘要： In the present invention a new method for program and program verify is described. The threshold voltage of the memory cell is shifted up and then measured with minimal charging and discharging of the bit lines and control gate lines. Bit line to control gate line capacitance is also used to reduce the number of voltage references needed. Program current is reduced by use of a load device coupled to the source diffusion. The result is increased program bandwidth with lower high voltage charge pump current consumption.

公开(公告)号：US06631089B1

公开(公告)日：2003-10-07

申请号：US10190636

申请日：2002-07-08

申请人： Nori Ogura ,  Tomoko Ogura

发明人： Nori Ogura ,  Tomoko Ogura

IPC分类号： G11C1606

CPC分类号： G11C16/0475 ,  G11C16/08

摘要： In the present invention a bit line decoder circuit a method of selecting bit lines for read and program operations is described for a twin MONOS memory cell array. A block of twin MONOS memory cells is partitioned into sub-blocks wherein decode signals select bit lines to be read and programmed, and select adjacent bit lines to provide bias for the read and program operations. The bit lines are partitioned into even and odd addresses within each sub-block, and an even and odd address sub-block selector connects the selected bit line along with adjacent bit lines to sense amplifiers and memory chip I/O.

摘要翻译： 在本发明中，对于双MONOS存储单元阵列描述了位线解码器电路，用于选择用于读取和编程操作的位线的方法。 双MONOS存储器单元的块被分割成子块，其中解码信号选择要被读取和编程的位线，并且选择相邻位线以提供读取和编程操作的偏置。 位线被划分成每个子块内的偶数和奇数地址，偶数和奇数地址子块选择器将所选位线与相邻位线连接到读出放大器和存储器芯片I / O。

公开(公告)号：US06549463B2

公开(公告)日：2003-04-15

申请号：US10016916

申请日：2001-12-14

申请人： Seiki Ogura ,  Tomoko Ogura ,  Nori Ogura

发明人： Seiki Ogura ,  Tomoko Ogura ,  Nori Ogura

IPC分类号： G11C1604

CPC分类号： G11C16/3459 ,  G11C16/0475 ,  G11C16/12 ,  G11C16/3454

摘要： In the present invention a new method for program and program verify is described. The threshold voltage of the memory cell is shifted up and then measured with minimal charging and discharging of the bit lines and control gate lines. Bit line to control gate line capacitance is also used to reduce the number of voltage references needed. Program current is reduced by use of a load device coupled to the source diffusion. The result is increased program bandwidth with lower high voltage charge pump current consumption.

公开(公告)号：US06542412B2

公开(公告)日：2003-04-01

申请号：US10058484

申请日：2002-01-28

申请人： Seiki Ogura ,  Tomoko Ogura

发明人： Seiki Ogura ,  Tomoko Ogura

IPC分类号： G11C1604

CPC分类号： H01L27/11521 ,  G11C11/5621 ,  G11C16/0425 ,  G11C16/0475 ,  G11C16/0491 ,  H01L27/115 ,  H01L27/11524

摘要： A fast program, ultra-high density, dual-bit, multi-level flash memory process, which can be applied to a ballistic step split gate side wall transistor, or to a ballistic planar split gate side wall transistor, which enables low voltage requirement on the floating gate during erase is described. Two side wall floating gates are paired with a single word line select gate, and word lines are arranged to be perpendicular to both the bit lines and control gate lines. Adjacent memory cells on the same word line share bitline diffusion as well as a third poly control gate. Control gates allow erase access to the individual floating gate.

摘要翻译： 一种快速程序，超高密度，双位，多级闪存过程，可应用于弹道分割栅侧壁晶体管，或可应用于弹道平面分裂栅侧壁晶体管，可实现低电压要求 在擦除时在浮动栅上进行描述。 两个侧壁浮动栅极与单个字线选择栅极配对，并且字线被布置成垂直于位线和控制栅极线。 相同字线上的相邻存储单元共享位线扩散以及第三个多路控制门。 控制门允许擦除访问各个浮动门。

公开(公告)号：US20130094299A1

公开(公告)日：2013-04-18

申请号：US13692503

申请日：2012-12-03

申请人： Nori Ogura ,  Tomoko Ogura ,  Seiki Ogura

发明人： Nori Ogura ,  Tomoko Ogura ,  Seiki Ogura

IPC分类号： G11C16/06 ,  G11C16/04

CPC分类号： G11C16/06 ,  G11C7/04 ,  G11C7/06 ,  G11C7/10 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/04 ,  G11C16/0466 ,  G11C16/10 ,  G11C2211/5647

摘要： Methods of complementary pairing of memory cells are described. These methods include two physical memory cells in a complementary pair, a complementary pair of reference cells for each erase block, and a physical complementary pair storing multiple data bits.

摘要翻译： 描述了存储器单元的互补配对的方法。 这些方法包括互补对中的两个物理存储器单元，每个擦除块的互补对参考单元，以及存储多个数据位的物理互补对。