发明授权
US06631089B1 Bit line decoding scheme and circuit for dual bit memory array 有权
双位存储器阵列的位线解码方案和电路

  • 专利标题: Bit line decoding scheme and circuit for dual bit memory array
  • 专利标题(中): 双位存储器阵列的位线解码方案和电路
  • 申请号: US10190636
    申请日: 2002-07-08
  • 公开(公告)号: US06631089B1
    公开(公告)日: 2003-10-07
  • 发明人: Nori OguraTomoko Ogura
  • 申请人: Nori OguraTomoko Ogura
  • 主分类号: G11C1606
  • IPC分类号: G11C1606
Bit line decoding scheme and circuit for dual bit memory array
摘要:
In the present invention a bit line decoder circuit a method of selecting bit lines for read and program operations is described for a twin MONOS memory cell array. A block of twin MONOS memory cells is partitioned into sub-blocks wherein decode signals select bit lines to be read and programmed, and select adjacent bit lines to provide bias for the read and program operations. The bit lines are partitioned into even and odd addresses within each sub-block, and an even and odd address sub-block selector connects the selected bit line along with adjacent bit lines to sense amplifiers and memory chip I/O.
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