发明授权
- 专利标题: Bit line decoding scheme and circuit for dual bit memory array
- 专利标题(中): 双位存储器阵列的位线解码方案和电路
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申请号: US10190636申请日: 2002-07-08
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公开(公告)号: US06631089B1公开(公告)日: 2003-10-07
- 发明人: Nori Ogura , Tomoko Ogura
- 申请人: Nori Ogura , Tomoko Ogura
- 主分类号: G11C1606
- IPC分类号: G11C1606
摘要:
In the present invention a bit line decoder circuit a method of selecting bit lines for read and program operations is described for a twin MONOS memory cell array. A block of twin MONOS memory cells is partitioned into sub-blocks wherein decode signals select bit lines to be read and programmed, and select adjacent bit lines to provide bias for the read and program operations. The bit lines are partitioned into even and odd addresses within each sub-block, and an even and odd address sub-block selector connects the selected bit line along with adjacent bit lines to sense amplifiers and memory chip I/O.
公开/授权文献
- US2106220A Baffle gate bearing for one-way rotation 公开/授权日:1938-01-25
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