公开(公告)号：US07092292B2

公开(公告)日：2006-08-15

申请号：US10976692

申请日：2004-10-28

Applicant: Nima Mokhlesi ,  Daniel C. Guterman ,  Geoffrey S. Gongwer

Inventor： Nima Mokhlesi ,  Daniel C. Guterman ,  Geoffrey S. Gongwer

IPC: G11C16/04

CPC classification number: G11C11/5642 ,  G11C16/0458 ,  G11C16/26

Abstract: The present invention presents methods for reducing the amount of noise inherent in the reading of a non-volatile storage device by applying an episodic agitation (e.g. a time varying voltage) to some terminal(s) of the cell as part of the reading process. Various aspects of the present invention also extend to devices beyond non-volatile memories. According to one aspect of the present invention, in addition to the normal voltage levels applied to the cell as part of the reading process, a time varying voltage is applied to the cell. A set of exemplary embodiments apply a single or multiple set of alternating voltages to one or more terminals of a floating gate memory cell just prior to or during the signal integration time of a read process. In other embodiments, other reproducible external or internal agitations which are repeatable, and whose average effect (from one integration time to the next integration time) remains sufficiently constant so as to have a net noise reduction effect is applicable.

公开(公告)号：US07403421B2

公开(公告)日：2008-07-22

申请号：US11426082

申请日：2006-06-23

Applicant: Nima Mokhlesi ,  Daniel C. Guterman ,  Geoffrey S. Gongwer

Inventor： Nima Mokhlesi ,  Daniel C. Guterman ,  Geoffrey S. Gongwer

IPC: G11C16/04

CPC classification number: G11C11/5642 ,  G11C16/0458 ,  G11C16/26

Abstract: The present invention presents methods for reducing the amount of noise inherent in the reading of a non-volatile storage device by applying an episodic agitation (e.g. a time varying voltage) to some terminal(s) of the cell as part of the reading process. Various aspects of the present invention also extend to devices beyond non-volatile memories. According to one aspect of the present invention, in addition to the normal voltage levels applied to the cell as part of the reading process, a time varying voltage is applied to the cell. A set of exemplary embodiments apply a single or multiple set of alternating voltages to one or more terminals of a floating gate memory cell just prior to or during the signal integration time of a read process. In other embodiments, other reproducible external or internal agitations which are repeatable, and whose average effect (from one integration time to the next integration time) remains sufficiently constant so as to have a net noise reduction effect is applicable.

Abstract translation: 本发明提供了用于通过在读取过程的一部分中对电池的一些或多个端子施加情景搅动（例如，时变电压）来减少读取非易失性存储装置中固有噪声的量的方法。 本发明的各个方面也扩展到超出非易失性存储器的设备。 根据本发明的一个方面，除了作为读取过程的一部分而施加到单元的正常电压电平之外，还对电池施加时变电压。 一组示例性实施例在读取过程的信号积分时间之前或期间将单个或多组交流电应用于浮动栅极存储器单元的一个或多个端子。 在其他实施例中，可重复的其他可再现的外部或内部搅拌以及其平均效应（从一个积分时间到下一个积分时间）保持足够恒定，以便具有净噪声降低效果。

公开(公告)号：US06850441B2

公开(公告)日：2005-02-01

申请号：US10052924

申请日：2002-01-18

Applicant: Nima Mokhlesi ,  Daniel C. Guterman ,  Geoffrey S. Gongwer

Inventor： Nima Mokhlesi ,  Daniel C. Guterman ,  Geoffrey S. Gongwer

IPC: G11C16/06 ,  G11C11/56 ,  G11C16/04 ,  G11C16/26

CPC classification number: G11C11/5642 ,  G11C16/0458 ,  G11C16/26

Abstract: The present invention presents methods for reducing the amount of noise inherent in the reading of a non-volatile storage device by applying an episodic agitation (e.g. a time varying voltage) to some terminal(s) of the cell as part of the reading process. Various aspects of the present invention also extend to devices beyond non-volatile memories. According to one aspect of the present invention, in addition to the normal voltage levels applied to the cell as part of the reading process, a time varying voltage is applied to the cell. A set of exemplary embodiments apply a single or multiple set of alternating voltages to one or more terminals of a floating gate memory cell just prior to or during the signal integration time of a read process. In other embodiments, other reproducible external or internal agitations which are repeatable, and whose average effect (from one integration time to the next integration time) remains sufficiently constant so as to have a net noise reduction effect is applicable.

Abstract translation: 本发明提供了用于通过在读取过程的一部分中对电池的一些或多个端子施加情景搅动（例如，时变电压）来减少读取非易失性存储装置中固有噪声的量的方法。 本发明的各个方面也扩展到超出非易失性存储器的设备。 根据本发明的一个方面，除了作为读取过程的一部分而施加到单元的正常电压电平之外，还对电池施加时变电压。 一组示例性实施例在读取过程的信号积分时间之前或期间将单个或多组交流电应用于浮动栅极存储器单元的一个或多个端子。 在其他实施例中，可重复的其他可再现的外部或内部搅拌以及其平均效应（从一个积分时间到下一个积分时间）保持足够恒定，以便具有净噪声降低效果。

公开(公告)号：US08014197B2

公开(公告)日：2011-09-06

申请号：US12604904

申请日：2009-10-23

Applicant: Nima Mokhlesi ,  Daniel C. Guterman

Inventor： Nima Mokhlesi ,  Daniel C. Guterman

IPC: G11C11/34

CPC classification number: G11C16/12 ,  G11C11/5628 ,  G11C11/5671 ,  G11C16/3459 ,  G11C16/3468 ,  G11C16/3481 ,  G11C2211/5621

Abstract: A system and method for quickly and efficiently programming hard-to-program storage elements in non-volatile integrated memory devices is presented. A number of storage elements are simultaneously subjected to a programming process with the current flowing through the storage elements limited to a first level. As a portion of these storage elements reach a prescribed state, they are removed from the set of cells being programmed and the current limit on the elements that continue to be programmed is raised. The current level in these hard-to-program cells can be raised to a second, higher limit or unregulated. According to another aspect, during a program operation the current limit allowed for a cell depends upon the target state to which it is to be programmed.

Abstract translation: 提出了一种用于在非易失性集成存储器件中快速高效地编程难编程存储元件的系统和方法。 多个存储元件同时进行编程处理，其中流过存储元件的电流限于第一级。 随着这些存储元件的一部分达到规定的状态，它们被从被编程的单元组移除，并且提高了继续编程的元件上的电流限制。 这些难以编程的单元格中的当前级别可以提高到第二个，更高的限制或不受管制。 根据另一方面，在程序操作期间，允许单元的电流限制取决于要被编程的目标状态。

公开(公告)号：US07068539B2

公开(公告)日：2006-06-27

申请号：US10766116

申请日：2004-01-27

Applicant: Daniel C. Guterman ,  Nima Mokhlesi ,  Yupin Fong

Inventor： Daniel C. Guterman ,  Nima Mokhlesi ,  Yupin Fong

IPC: G11C11/34

CPC classification number: G11C11/5628 ,  G11C16/10 ,  G11C2211/5621 ,  G11C2211/5624

Abstract: A non-volatile memory device is programmed by first performing a coarse programming process and subsequently performing a fine programming process. The coarse/fine programming methodology is enhanced by using an efficient verification scheme that allows some non-volatile memory cells to be verified for the coarse programming process while other non-volatile memory cells are verified for the fine programming process. The fine programming process can be accomplished using current sinking, charge packet metering or other suitable means.

公开(公告)号：US07630237B2

公开(公告)日：2009-12-08

申请号：US11196547

申请日：2005-08-02

Applicant: Nima Mokhlesi ,  Daniel C. Guterman

Inventor： Nima Mokhlesi ,  Daniel C. Guterman

IPC: G11C11/34

CPC classification number: G11C16/12 ,  G11C11/5628 ,  G11C11/5671 ,  G11C16/3459 ,  G11C16/3468 ,  G11C16/3481 ,  G11C2211/5621

Abstract: A system and method for quickly and efficiently programming hard-to-program storage elements in non-volatile integrated memory devices is presented. A number of storage elements are simultaneously subjected to a programming process with the current flowing through the storage elements limited to a first level. As a portion of these storage elements reach a prescribed state, they are removed from the set of cells being programmed and the current limit on the elements that continue to be programmed is raised. The current level in these hard-to-program cells can be raised to a second, higher limit or unregulated. According to another aspect, during a program operation the current limit allowed for a cell depends upon the target state to which it is to be programmed.

Abstract translation: 提出了一种用于在非易失性集成存储器件中快速高效地编程难编程存储元件的系统和方法。 多个存储元件同时进行编程处理，其中流过存储元件的电流限于第一级。 随着这些存储元件的一部分达到规定的状态，它们被从被编程的单元组移除，并且提高了继续编程的元件上的电流限制。 这些难以编程的单元格中的当前级别可以提高到第二个，更高的限制或不受管制。 根据另一方面，在程序操作期间，允许单元的电流限制取决于要被编程的目标状态。

公开(公告)号：US07301812B2

公开(公告)日：2007-11-27

申请号：US11392901

申请日：2006-03-29

Applicant: Daniel C. Guterman ,  Nima Mokhlesi ,  Yupin Fong

Inventor： Daniel C. Guterman ,  Nima Mokhlesi ,  Yupin Fong

IPC: G11C16/04

CPC classification number: G11C16/0483 ,  G11C16/12 ,  G11C16/30 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3454 ,  G11C16/3459

Abstract: A system is disclosed for programming non-volatile memory with greater precision. In one embodiment, the system includes applying a first phase of a boosting signal to one or more unselected word lines for a set of NAND strings, applying a programming level to selected bit lines of the NAND strings while applying the first phase of the boosting signal, and applying an inhibit level to unselected bit lines of the NAND strings while applying the first phase of the boosting signal. Subsequently, a second phase of the boosting signal is applied to the one or more unselected word lines and the signal(s) on the selected bit lines are changed by applying the inhibit level to the selected bit lines so that NAND strings associated with the selected bit lines will be boosted by the second phase of the boosting signal. A program voltage signal is applied to a selected word line in order to program storage elements connected to the selected word line.

Abstract translation: 公开了一种更精确地编程非易失性存储器的系统。 在一个实施例中，该系统包括将一个升压信号的第一相位应用于一组NAND串的一个或多个未选字线，将编程电平施加到NAND串的选定位线，同时施加升压信号的第一相位 并且在施加升压信号的第一相位时将禁止电平施加到NAND串的未选位线。 随后，将升压信号的第二相位施加到一个或多个未选字线，并且通过将所述禁止电平施加到所选择的位线来改变所选位线上的信号，使得与所选择的位线相关联的NAND串 位线将由升压信号的第二阶段提升。 将程序电压信号施加到所选择的字线，以便编程连接到所选字线的存储元件。

公开(公告)号：US07447075B2

公开(公告)日：2008-11-04

申请号：US11429770

申请日：2006-05-08

Applicant: Daniel C. Guterman ,  Nima Mokhlesi ,  Yupin Fong

Inventor： Daniel C. Guterman ,  Nima Mokhlesi ,  Yupin Fong

IPC: G11C11/34

CPC classification number: G11C11/5628 ,  G11C16/10 ,  G11C2211/5621 ,  G11C2211/5624

Abstract: A non-volatile memory device is programmed by first performing a coarse programming process and subsequently performing a fine programming process. The coarse/fine programming methodology is enhanced by using an efficient verification scheme that allows some non-volatile memory cells to be verified for the coarse programming process while other non-volatile memory cells are verified for the fine programming process. The fine programming process can be accomplished using current sinking, charge packet metering or other suitable means.

Abstract translation: 通过首先执行粗略编程处理并随后执行精细编程处理来编程非易失性存储器件。 通过使用有效的验证方案来增强粗/精编程方法，该验证方案允许对粗略编程过程验证一些非易失性存储器单元，同时验证其它非易失性存储器单元用于精细编程过程。 精细的编程过程可以使用电流吸收，电荷分组测量或其他合适的方法来完成。

公开(公告)号：US07317638B2

公开(公告)日：2008-01-08

申请号：US11550502

申请日：2006-10-18

Applicant: Daniel C. Guterman ,  Nima Mokhlesi ,  Yupin Fong

Inventor： Daniel C. Guterman ,  Nima Mokhlesi ,  Yupin Fong

IPC: G11C16/12 ,  G11C16/10 ,  G11C16/28 ,  G11C16/26

CPC classification number: G11C16/3459 ,  G11C11/5628 ,  G11C16/3454 ,  G11C16/3481 ,  G11C2211/5621 ,  G11C2211/5624

Abstract: A non-volatile memory device is programmed by first performing a coarse programming process and subsequently performing a fine programming process. The coarse/fine programming methodology is enhanced by using an efficient verification scheme that allows some non-volatile memory cells to be verified for the coarse programming process while other non-volatile memory cells are verified for the fine programming process. The fine programming process can be accomplished using current sinking, charge packet metering or other suitable means.

Abstract translation: 通过首先执行粗略编程处理并随后执行精细编程处理来编程非易失性存储器件。 通过使用有效的验证方案来增强粗/精编程方法，该验证方案允许对粗略编程过程验证一些非易失性存储器单元，同时验证其它非易失性存储器单元用于精细编程过程。 精细的编程过程可以使用电流吸收，电荷分组测量或其他合适的方法来完成。

公开(公告)号：US07139198B2

公开(公告)日：2006-11-21

申请号：US10766217

申请日：2004-01-27

Applicant: Daniel C. Guterman ,  Nima Mokhlesi ,  Yupin Fong

Inventor： Daniel C. Guterman ,  Nima Mokhlesi ,  Yupin Fong

IPC: G11C16/34 ,  G11C16/10

CPC classification number: G11C16/3459 ,  G11C11/5628 ,  G11C16/3454 ,  G11C16/3481 ,  G11C2211/5621 ,  G11C2211/5624

Abstract: A non-volatile memory device is programmed by first performing a coarse programming process and subsequently performing a fine programming process. The coarse/fine programming methodology is enhanced by using an efficient verification scheme that allows some non-volatile memory cells to be verified for the coarse programming process while other non-volatile memory cells are verified for the fine programming process. The fine programming process can be accomplished using current sinking, charge packet metering or other suitable means.

Abstract translation: 通过首先执行粗略编程处理并随后执行精细编程处理来编程非易失性存储器件。 通过使用有效的验证方案来增强粗/精编程方法，该验证方案允许对粗略编程过程验证一些非易失性存储器单元，同时验证其它非易失性存储器单元用于精细编程过程。 精细的编程过程可以使用电流吸收，电荷分组测量或其他合适的方法来完成。