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公开(公告)号：US10211840B2
公开(公告)日：2019-02-19
申请号：US15410890
申请日：2017-01-20
申请人： NXP USA, Inc.
摘要： A charge pump driver circuit comprises an output stage and a current generator component. The output stage is arranged to receive at an input node thereof a control current signal and comprises a resistance network coupled between the input node thereof and a reference voltage node and arranged to provide a resistive path through which the control current signal flows. The output stage is arranged to generate at an output node thereof a charge pump control voltage signal based on the voltage level at the input node thereof. The current generator component is arranged to receive an indication of a voltage level of a charge pump output signal, and to generate a feedback current dependent on the voltage level of the output signal, wherein the feedback current is injected into the resistive path of the resistance network through which the control current signal flows.
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公开(公告)号：US09973360B2
公开(公告)日：2018-05-15
申请号：US15366273
申请日：2016-12-01
申请人： NXP USA, Inc.
CPC分类号： H04L27/0014 , G06F7/5446 , G06F7/548 , H04L27/206 , H04L2027/0016
摘要： A phase shifter controller arranged to generate phase shift control signals for at least one phase shifter. The phase shifter controller is arranged to receive a first phase value θ1, receive a second phase value θ2, and output phase shift control signals. The phase shifter controller comprises a digital synthesizer arranged to compute a first digital phase shift control value based on the received first phase value θ1, and compute a second digital phase shift control value based on the received second phase value θ2. The phase shifter controller further comprises digital to analogue converters arranged to generate the phase shift control signals based on the derived first and second digital phase shift control values.
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公开(公告)号：US20200003882A1
公开(公告)日：2020-01-02
申请号：US16447908
申请日：2019-06-20
申请人： NXP USA, Inc.
发明人： Didier Salle , Cristian Pavao Moreira , Dominique Delbecq , Olivier Doaré , Jean-Stephane Vigier , Birama Goumballa
摘要： A communication unit (300) is described that includes a plurality of cascaded devices that includes at least one master device and at least one slave device configured in a master-slave arrangement. The at least one master device comprises a modulator circuit (362) configured to: receive a system clock signal and a frame start signal; modulate the system clock signal with the frame start signal to produce a modulated master-slave clock signal (384); and transmit the modulated master-slave clock signal (384) to the at least one slave device. The at least one slave device comprises a demodulator circuit (364) configured to: receive and demodulate the modulated master-slave clock signal (384); and re-create therefrom the system clock signal (388, 385) and the frame start signal (390, 386).
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公开(公告)号：US20170180169A1
公开(公告)日：2017-06-22
申请号：US15366273
申请日：2016-12-01
申请人： NXP USA, Inc.
CPC分类号： H04L27/0014 , G06F7/5446 , G06F7/548 , H04L27/206 , H04L2027/0016
摘要： A phase shifter controller arranged to generate phase shift control signals for at least one phase shifter. The phase shifter controller is arranged to receive a first phase value θ1, receive a second phase value θ2, and output phase shift control signals. The phase shifter controller comprises a digital synthesizer arranged to compute a first digital phase shift control value based on the received first phase value θ1, and compute a second digital phase shift control value based on the received second phase value θ2. The phase shifter controller further comprises digital to analogue converters arranged to generate the phase shift control signals based on the derived first and second digital phase shift control values.
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公开(公告)号：US11796635B2
公开(公告)日：2023-10-24
申请号：US17391278
申请日：2021-08-02
申请人： NXP USA, INC.
CPC分类号： G01S7/4008 , G01S7/4021 , G01S13/26 , H03H11/16
摘要： The disclosure relates to a radar transceiver having a transmitter comprising a phase shifter. Example embodiments include a radar transceiver (200) having a normal mode of transmitter operation and a self-test mode of operation, the transceiver (200) comprising: a digital controller (116) configured to provide a digital control signal indicative of a phase shift; a digital to analogue converter (122) configured to receive the digital control signal and provide an analogue signal in accordance with the phase shift; a phase shifter (124) configured to receive the analogue signal and provide a phase shifted output signal for transmission; a dummy load (240) connected to receive the analogue signal from the digital to analogue converter (122) and to provide an analogue output; a resistor network (331) connected across an output of the dummy load (240); a testing module (335) configured to measure the analogue output of the dummy load (240); and a controller module (339) configured to control operation of the dummy load (240), testing module (335) and digital controller (116) during the self-test mode of operation by: enabling the dummy load (240); operating the digital controller (116) to provide a range of digital control signals to the digital to analogue converter (122); and operate the testing module (335) to measure the analogue output of the dummy load (240) to determine a measure of linearity of the digital to analogue converter (122).
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公开(公告)号：US11652470B2
公开(公告)日：2023-05-16
申请号：US17204290
申请日：2021-03-17
申请人： NXP USA, INC.
发明人： Dominique Delbecq , Julien Orlando
CPC分类号： H03H11/16 , H03H11/04 , H03K5/01 , H03K2005/00286
摘要： A phase rotator control circuit is provided. The phase rotator control circuit is coupled to a phase rotator core and includes a first set of transistors coupled to receive digital control signals. The first set of transistors is coupled to a second set of transistors configured and arranged to form a filtered current mirror. An output of the filtered current mirror is coupled to provide an analog phase control signal to the phase rotator core.
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公开(公告)号：US20220021378A1
公开(公告)日：2022-01-20
申请号：US17361590
申请日：2021-06-29
申请人： NXP USA, INC.
IPC分类号： H03K5/01
摘要： A phase rotator calibration system is provided. The phase rotator calibration system includes a phase rotator portion having input for receiving an input signal and an output for providing an output signal. A calibration portion is coupled to the phase rotator portion. The calibration portion is configured to determine a phase error based on a phase estimation. The phase estimation is generated by way of an arccosine function.
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公开(公告)号：US20210305969A1
公开(公告)日：2021-09-30
申请号：US17204290
申请日：2021-03-17
申请人： NXP USA, INC.
发明人： Dominique Delbecq , Julien Orlando
摘要： A phase rotator control circuit is provided. The phase rotator control circuit is coupled to a phase rotator core and includes a first set of transistors coupled to receive digital control signals. The first set of transistors is coupled to a second set of transistors configured and arranged to form a filtered current mirror. An output of the filtered current mirror is coupled to provide an analog phase control signal to the phase rotator core.
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公开(公告)号：US20200057140A1
公开(公告)日：2020-02-20
申请号：US15999181
申请日：2018-08-17
申请人： NXP USA, Inc.
摘要： A chirp linearity detector, integrated circuit, and method are provided. The chirp linearity detector comprises a phase-locked loop (PLL) frequency sampling circuit and a frequency sweep linearity measuring circuit. The PLL frequency sampling circuit comprises a frequency divider circuit for receiving a PLL output signal from a PLL and for providing a frequency divided output signal, a first low pass filter circuit for receiving the frequency divided output signal, for reducing harmonic mixing, and for providing a mixer input signal, a mixer circuit for receiving the mixer input signal, for mixing the mixer input signal with a local oscillator signal, and for providing a mixer output signal, a second low pass filter circuit for performing anti-aliasing filtering and for providing an analog-to-digital converter (ADC) input signal, and an ADC circuit for digitizing the ADC input signal and for providing a digital output signal.
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公开(公告)号：US20180121282A1
公开(公告)日：2018-05-03
申请号：US15705332
申请日：2017-09-15
申请人： NXP USA, Inc.
发明人： Andres Barrilado Gonzalez , Ralf Reuter , Dominique Delbecq , Francesco d'Esposito , Arnaud Sion , Gustavo Adolfo Guarin Aristizabal , Marcel Christoph Welpot
CPC分类号： G06F11/1004 , G06F3/0619 , G06F3/064 , G06F3/0683 , G06F11/08 , G06F11/10
摘要： A system for register error detection is described, the system comprising: a plurality of addressable registers comprising sets of registers, the registers in each set having contiguous addresses; a cyclic redundancy check generator coupled to the addressable registers and configured to determine a cyclic-redundancy-check result for each set of registers from the values of each of the respective set of registers; a controller coupled to the registers and the cyclic-redundancy-check generator. The controller comprises a cyclic-redundancy-check calculator and is configured to determine an expected cyclic-redundancy-check result from expected values for each of the set of registers, to read the cyclic-redundancy-check result for each of the set of registers determined by the cyclic-redundancy-check generator, and to compare the generated cyclic-redundancy-check result with the calculated cyclic-redundancy-check result and wherein a difference between the generated cyclic-redundancy-check result and the calculated cyclic-redundancy-check result is indicative of an error condition.
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