Encoding/decoding system for parallel data

    公开(公告)号:US10193566B2

    公开(公告)日:2019-01-29

    申请号:US14428084

    申请日:2013-09-06

    Abstract: An object is to enable erasure correction even at the time of a degeneration operation and reduce the number of necessary parallel media through dynamic setting of degree of redundancy. A parallel data encoding/decoding system performs parallel data transmissions using a plurality of lanes from an encoder to a decoder. The encoder encodes products of elements of an encoding vector M of symbols of each lane and a state vector U indicating validity of the symbols, and transmits the state vector U along with a transmission vector Y obtained through the encoding. The decoder decodes a subset Msub constituted of valid elements of the encoding vector M using a received reception vector Y′, the received state vector U, and an erasure vector E indicating whether each element of the transmission vector has been erased in a transmission/reception section.

    Transmission apparatus and transmission system

    公开(公告)号:US11923862B2

    公开(公告)日:2024-03-05

    申请号:US17311646

    申请日:2019-12-04

    CPC classification number: H03L7/18 H04B1/04 H04B1/06 H04J3/062 H04J3/14 H04L7/0037

    Abstract: A first reception processing unit performs a process of receiving a first signal transmitted on a first transmission line, a second reception processing unit performs a process of receiving a second signal transmitted on a second transmission line, and an output speed control unit controls output speeds of the first signal and the second signal subjected to the reception process. A system switching unit selects and outputs the first signal or the second signal subjected to a reception process, and an output processing unit performs a process for output to another apparatus on the output from the system switching unit. A reception side clock output unit outputs a clock signal giving a processing timing of each process, and a clock frequency control unit adjusts a frequency of the clock signal giving the processing timing to the output processing unit. A frequency adjustment range calculation unit calculates an adjustment range of the frequency based on frequency deviation accuracy of the reception side clock output unit, frequency deviation accuracy of a transmission side clock output unit that outputs a clock signal giving a processing timing to a transmission process at a transmission apparatus on the transmission side, and a prescribed value of a frequency deviation.

    ENCODING/DECODING SYSTEM FOR PARALLEL DATA
    10.
    发明申请
    ENCODING/DECODING SYSTEM FOR PARALLEL DATA 审中-公开
    并行数据编码/解码系统

    公开(公告)号:US20150229329A1

    公开(公告)日:2015-08-13

    申请号:US14428084

    申请日:2013-09-06

    Abstract: An object is to enable erasure correction even at the time of a degeneration operation and reduce the number of necessary parallel media through dynamic setting of degree of redundancy. A parallel data encoding/decoding system performs parallel data transmissions using a plurality of lanes from an encoder to a decoder. The encoder encodes products of elements of an encoding vector M of symbols of each lane and a state vector U indicating validity of the symbols, and transmits the state vector U along with a transmission vector Y obtained through the encoding. The decoder decodes a subset Msub constituted of valid elements of the encoding vector M using a received reception vector Y′, the received state vector U, and an erasure vector E indicating whether each element of the transmission vector has been erased in a transmission/reception section.

    Abstract translation: 目的是即使在退化操作时也能够进行擦除校正,并且通过动态设置冗余度来减少所需的并行介质的数量。 并行数据编码/解码系统使用从编码器到解码器的多个通道来执行并行数据传输。 编码器对每个通道的符号的编码矢量M的元素的乘积和表示符号的有效性的状态向量U进行编码,并且将状态矢量U与通过编码获得的发送矢量Y一起发送。 解码器使用接收到的接收矢量Y',接收状态向量U和指示传输矢量的每个要素是否在发送/接收中被擦除的擦除矢量E来解码由编码矢量M的有效元素构成的子集Msub 部分。

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