公开(公告)号：US11916019B2

公开(公告)日：2024-02-27

申请号：US17582205

申请日：2022-01-24

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Te-Yin Chen

IPC分类号： H01L23/538 ,  H01L21/768 ,  H01L23/525 ,  H01L23/532

CPC分类号： H01L23/5384 ,  H01L21/76841 ,  H01L23/5252 ,  H01L23/5254 ,  H01L23/53266

摘要： The present application discloses a method for fabricating a semiconductor device. The method includes providing a substrate, forming a first conductive layer above the substrate, concurrently forming a bottom conductive layer and a redistribution structure above the first conductive layer, forming a programmable insulating layer on the bottom conductive layer, and forming a top conductive layer on the programmable insulating layer. The bottom conductive layer, the programmable insulating layer, and the top conductive layer together configure a programmable unit. The bottom conductive layer and the redistribution structure are electrically coupled to the first conductive layer.

公开(公告)号：US11488907B2

公开(公告)日：2022-11-01

申请号：US17107001

申请日：2020-11-30

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Te-Yin Chen

IPC分类号： H01L23/538 ,  H01L21/768 ,  H01L23/532 ,  H01L23/525

摘要： The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a first conductive layer positioned above the substrate, a bottom conductive layer positioned above the first conductive layer and electrically coupled to the first conductive layer, a programmable insulating layer positioned on the bottom conductive layer, a top conductive layer positioned on the programmable insulating layer, and a redistribution structure positioned above the first conductive layer and electrically coupled to the first conductive layer. The bottom conductive layer, the programmable insulating layer, and the top conductive layer together configure a programmable unit.

公开(公告)号：US11955564B2

公开(公告)日：2024-04-09

申请号：US17582230

申请日：2022-01-24

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Te-Yin Chen

IPC分类号： H01L29/788 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L27/092

CPC分类号： H01L29/788 ,  H01L29/42328 ,  H01L29/4983 ,  H01L29/512 ,  H01L29/66825 ,  H01L27/092

摘要： The present application discloses a method for fabricating a semiconductor device with an oxidized intervention layer. The method includes providing a substrate; forming a tunneling insulating layer over the substrate; forming a floating gate over the tunnel oxide layer; forming a dielectric layer over the floating gate; forming a control gate over the dielectric layer; and performing a lateral oxidation process over the substrate, wherein a process temperature of the lateral oxidation process is between about 300° C. and about 600° C.

公开(公告)号：US11700720B2

公开(公告)日：2023-07-11

申请号：US17828264

申请日：2022-05-31

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Te-Yin Chen

IPC分类号： H01L23/485 ,  H10B12/00 ,  H01L21/768

CPC分类号： H10B12/0335 ,  H01L21/7682 ,  H01L21/76885 ,  H10B12/315 ,  H10B12/34

摘要： The present application provides a memory device with an air gap. The memory device includes an active region disposed in a substrate; a word line disposed in the substrate, wherein the word line is intersected with the active region; a contact structure disposed on the substrate, wherein the contact structure is located at a side of the word line, and electrically connected to the active region; a first conductive layer and a second conductive layer disposed over the substrate, wherein the contact structure is covered by the first and second conductive layers; a conductive pillar overlapped with and electrically connected to the contact structure; a landing pad covers and electrically connects to the conductive pillar, wherein a sidewall of the conductive pillar is laterally recessed from a sidewall of the landing pad; and a dielectric layer laterally surrounding the conductive pillar and the landing pad.

公开(公告)号：US11296211B2

公开(公告)日：2022-04-05

申请号：US16910833

申请日：2020-06-24

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Te-Yin Chen

IPC分类号： H01L29/66 ,  H01L29/417 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/027

摘要： A method for preparing a semiconductor device includes forming a ring structure over a semiconductor substrate, and etching the semiconductor substrate by using the ring structure as a mask to form an annular semiconductor fin. The method also includes epitaxially growing a first bottom source/drain structure within the annular semiconductor fin and a second bottom source/drain structure surrounding the annular semiconductor fin. The method further includes forming a first silicide layer over the first bottom source/drain structure and a second silicide layer over the second bottom source/drain structure. In addition, the method includes forming a first gate structure over the first silicide layer and a second gate structure over the second silicide layer, and epitaxially growing a top source/drain structure over the annular semiconductor fin.

公开(公告)号：US12119302B2

公开(公告)日：2024-10-15

申请号：US17698509

申请日：2022-03-18

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Te-Yin Chen

IPC分类号： H01L23/535 ,  H01L21/768 ,  H01L23/532

CPC分类号： H01L23/535 ,  H01L21/76805 ,  H01L21/7682 ,  H01L21/76843 ,  H01L21/76895 ,  H01L23/5329

摘要： The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate having plurality of contacts, a plurality of composite plugs positioned above the plurality of contacts, a plurality of metal spacers positioned above the substrate; and a plurality of air gaps positioned above the substrate. At least one of the plurality of composite plugs includes a protection liner having a U-shaped profile and a metal plug in the protection liner, and the protection liner is in direct contact with one of the plurality of contacts.

公开(公告)号：US11621265B2

公开(公告)日：2023-04-04

申请号：US17380745

申请日：2021-07-20

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Te-Yin Chen

IPC分类号： H10B12/00 ,  H01L21/768 ,  H01L27/108

摘要： The present application discloses a method for fabricating a semiconductor device with a self-aligned landing pad. The method includes: providing a substrate; forming a dielectric layer with a plug over the substrate; performing an etching process to remove a portion of the dielectric layer to expose a protruding portion of the plug; forming a liner layer covering the dielectric layer and the protruding portion; and performing a thermal process to form a landing pad over the dielectric layer. The landing pad comprises a protruding portion of the plug, a first silicide layer disposed over the protruding portion, and a second silicide layer disposed on a sidewall of the protruding portion.

公开(公告)号：US11469233B2

公开(公告)日：2022-10-11

申请号：US16912255

申请日：2020-06-25

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Te-Yin Chen

IPC分类号： H01L21/71 ,  H01L27/108 ,  H01L21/768

摘要： The present application provides a method for preparing a memory device. The method includes: forming an active region in a substrate, forming a word line in the substrate, wherein the word line is intersected with the active region; forming a contact structure on the substrate, wherein the contact structure is located at a side of the word line, and electrically connected to the active region; sequentially forming a first conductive layer and a second conductive layer over the substrate, wherein the contact structure is covered by the first and second conductive layers; patterning the first and second conductive layers to form a conductive pillar and a landing pad, respectively, wherein the conductive pillar is overlapped with and electrically connected to the contact structure, the landing pad covers and electrically connects to the conductive pillar, and a sidewall of the conductive pillar is laterally recessed from a sidewall of the landing pad; and forming a dielectric layer to laterally surround the conductive pillar and the landing pad.

公开(公告)号：US11777012B2

公开(公告)日：2023-10-03

申请号：US17563276

申请日：2021-12-28

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Te-Yin Chen

IPC分类号： H01L29/66 ,  H01L29/417 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/027

CPC分类号： H01L29/66666 ,  H01L21/027 ,  H01L21/823431 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7827

摘要： A method for preparing a semiconductor device includes forming a ring structure over a semiconductor substrate, and etching the semiconductor substrate by using the ring structure as a mask to form an annular semiconductor fin. The method also includes epitaxially growing a first bottom source/drain structure within the annular semiconductor fin and a second bottom source/drain structure surrounding the annular semiconductor fin. The method further includes forming a first silicide layer over the first bottom source/drain structure and a second silicide layer over the second bottom source/drain structure. In addition, the method includes forming a first gate structure over the first silicide layer and a second gate structure over the second silicide layer, and epitaxially growing a top source/drain structure over the annular semiconductor fin.

公开(公告)号：US10991702B2

公开(公告)日：2021-04-27

申请号：US16413261

申请日：2019-05-15

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Te-Yin Chen

IPC分类号： H01L27/108 ,  H01L21/762 ,  H01L21/265 ,  H01L21/308 ,  H01L29/40 ,  H01L21/311 ,  H01L21/8234

摘要： The present disclosure provide a semiconductor device and a method for preparing the semiconductor device. The semiconductor device includes a substrate having a memory cell region and a peripheral region, wherein the memory cell region has at least one first shallow trench isolation and the peripheral region has at least one second shallow trench isolation; a plurality of gates in the first shallow trench isolation; a first semiconductor layer in the peripheral region; a first insulating layer covering the substrate in the memory cell region; a crystalline overlayer in the memory cell region and a doped portion of the substrate below the crystalline overlayer; and a second semiconductor layer on a portion of the first insulating layer, wherein a top surface of the first semiconductor layer and a top surface of the second semiconductor layer are coplanar.