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公开(公告)号:US20230336503A1
公开(公告)日:2023-10-19
申请号:US17721771
申请日:2022-04-15
Applicant: Microsoft Technology Licensing, LLC
Inventor: Shachar RAINDEL
IPC: H04L49/90
CPC classification number: H04L49/9036 , H04L49/9084 , H04L49/9068
Abstract: Embodiments of the present disclosure include techniques for receiving and processing packets. A program configures a network interface to store data from each received packet in one or more packet buffers. If data from a packet exceeds the capacity of the assigned packet buffers, remaining data from the packet may be stored in an overflow buffer. The packet may then be deleted efficiently without delays resulting from handling the remaining data.
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公开(公告)号:US20230261960A1
公开(公告)日:2023-08-17
申请号:US18306582
申请日:2023-04-25
Applicant: MICROSOFT TECHNOLOGY LICENSING, LLC
Inventor: Shachar RAINDEL , Jitendra D. PADHYE , Avi William LEVY , Mahmoud S. EL HADDAD , Alireza KHOSGOFTAR MONAFARED , Brian D. ZILL , Behnaz ARZANI , Xinchen GUO
IPC: H04L43/106 , H04L41/0631 , H04L43/16 , H04L43/0817 , H04L45/02 , H04L41/00 , H04L41/0677
CPC classification number: H04L43/106 , H04L41/0631 , H04L43/16 , H04L43/0817 , H04L45/02 , H04L41/30 , H04L41/064 , H04L41/0677 , H04L43/0852
Abstract: Techniques are disclosed for identifying faulty links in a virtualized computing environment. Network path latency information is received for one or more network paths in the networked computing environment. Based on the network path latency information, a probable presence of a faulty component is determined. In response to the determination, physical links for a network path associated with the probable faulty component are identified. Information indicative of likely sources of the probable faulty component is received from multiple hosts of the networked computing environment. Based on the identified physical links and information, a faulty component is determined.
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公开(公告)号:US20240004683A1
公开(公告)日:2024-01-04
申请号:US17853655
申请日:2022-06-29
Applicant: Microsoft Technology Licensing, LLC
Inventor: Shachar RAINDEL , Daniel Sebastian BERGER
IPC: G06F9/455
CPC classification number: G06F9/45558 , G06F2009/4557
Abstract: Solutions for scheduling page migrations use latency tolerance of coupled devices, such as external peripheral devices (e.g., network adapters), to prevent buffer overflows or other negative performance. A latency tolerance of a device coupled to a virtual object, such as a virtual machine (VM) is determined. This may include the device exposing its latency tolerance using latency tolerance reporting (LTR). When a page migration for the virtual object is pending, a determination is made whether sufficient time exists to perform the page migration, based on at least the latency tolerance of the device. The page migration is performed if sufficient time exists. Otherwise, the page migration is delayed. In some examples, latency tolerances of multiple devices are considered. In some examples, multiple page migrations are performed contemporaneously, based on latency tolerances. Various options are disclosed, such as the page migration being performed by the virtual object software or the device.
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公开(公告)号:US20230305968A1
公开(公告)日:2023-09-28
申请号:US17706044
申请日:2022-03-28
Applicant: Microsoft Technology Licensing, LLC
Inventor: Ramakrishna HUGGAHALLI , Shachar RAINDEL
IPC: G06F12/128 , G06F12/0811 , G06F12/0804 , G06F9/30
CPC classification number: G06F12/128 , G06F12/0811 , G06F12/0804 , G06F9/30047 , G06F9/30101
Abstract: Embodiments of the present disclosure includes techniques for cache memory replacement in a processing unit. A first data production operation to store first data to a first cache line of the cache memory is detected at a first time. A retention status of the first cache line is updated to a first retention level as a result of the first data production operation. Protection against displacement of the first data in the first cache line is increased based on the first retention level. A first data consumption operation retrieving the first data from the first cache line is detected at a second time after the first time. The retention status of the first cache line is updated to a second retention level as a result of the first data consumption operation, the second retention level being a lower level of retention than the first retention level.
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公开(公告)号:US20230305739A1
公开(公告)日:2023-09-28
申请号:US17706088
申请日:2022-03-28
Applicant: Microsoft Technology Licensing, LLC
Inventor: Ramakrishna HUGGAHALLI , Shachar RAINDEL
IPC: G06F3/06
CPC classification number: G06F3/0655 , G06F3/0604 , G06F3/0679
Abstract: Embodiments of the present disclosure includes techniques for partial memory updates in a computer system. A data structure template is received. A first write data of a first write operation is received from a first data source, the first write operation performed in connection with provisioning of a first data payload to memory communicatively coupled with a processing unit. A first merge operation is performed involving the first write data and the first data structure template to obtain a first data structure update. The first data structure update is written to the memory, thereby improving efficiency of updating a first data structure associated with the first data payload.
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公开(公告)号:US20220360511A1
公开(公告)日:2022-11-10
申请号:US17812525
申请日:2022-07-14
Applicant: MICROSOFT TECHNOLOGY LICENSING, LLC
Inventor: Shachar RAINDEL
IPC: H04L43/0864 , H04L43/10 , H04L43/0817 , H04L43/0894
Abstract: Techniques for network latency estimation in a computer network are disclosed herein. One example technique includes instructing first and second nodes in the computer network to individually perform traceroute operations along a first round-trip route and a second round-trip route between the first and second nodes. The first round-trip route includes an inbound network path of an existing round-trip route between the first and second nodes and an outbound network path that is a reverse of the inbound network path. The second round-trip route has an outbound network path of the existing round-trip route and an inbound network path that is a reverse of the outbound network path. The example technique further includes upon receiving traceroute information from the additional traceroute operations, determine a latency difference between the inbound and outbound network paths of the existing round-trip route based on the received additional traceroute information.
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公开(公告)号:US20240056361A1
公开(公告)日:2024-02-15
申请号:US17887081
申请日:2022-08-12
Applicant: Microsoft Technology Licensing, LLC
Inventor: Wei BAI , Jitendra PADHYE , Shachar RAINDEL , Zhuolong YU , Mahmoud ELHADDAD , Abdul KABBANI
IPC: H04L41/14 , H04L41/0803 , H04L41/22 , H04L41/00 , H04L67/1095 , H04L43/045
CPC classification number: H04L41/145 , H04L41/0803 , H04L41/22 , H04L41/24 , H04L67/1095 , H04L43/045
Abstract: This document relates to analyzing of network stack functionality that is implemented in hardware, such as on a network adapter. The disclosed implementations employ a programmable network device, such as a switch, to inject events into traffic and mirror the traffic for subsequent analysis. The events can have user-specified event parameters to test different types of network stack behavior, such as how the network adapters respond to corrupted packets, dropped packets, or explicit congestion notifications.
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公开(公告)号:US20230401160A1
公开(公告)日:2023-12-14
申请号:US17836936
申请日:2022-06-09
Applicant: Microsoft Technology Licensing, LLC
Inventor: Ramakrishna HUGGAHALLI , Shachar RAINDEL
IPC: G06F12/1045 , G06F12/0862 , G06F12/06 , G06F12/02
CPC classification number: G06F12/1063 , G06F12/1054 , G06F12/0862 , G06F12/063 , G06F12/0238
Abstract: In one example of the present technology, an input/output memory management unit (IOMMU) of a computing device is configured to: receive a prefetch message including a virtual address from a central processing unit (CPU) core of a processor of the computing device; perform a page walk on the virtual address through a page table stored in a main memory of the computing device to obtain a prefetched translation of the virtual address to a physical address; and store the prefetched translation of the virtual address to the physical address in a translation lookaside buffer (TLB) of the IOMMU.
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公开(公告)号:US20180067893A1
公开(公告)日:2018-03-08
申请号:US15622787
申请日:2017-06-14
Applicant: Microsoft Technology Licensing, LLC
Inventor: Shachar RAINDEL , Anirudh Badam , Jitendra Padhye
IPC: G06F15/173 , G06F13/28 , G06F13/42
CPC classification number: G06F15/17331 , G06F13/28 , G06F13/287 , G06F13/4282 , G06F2213/0024
Abstract: An originating host device in a distribution chain is provided upstream from multiple host devices including intermediary and terminating host devices. The originating host device includes a core with a generation application and a first RDMA NIC. The core: determines a plan for transferring data between the originating host device and the other host devices; and generates WQEs to implement the plan. The first RDMA NIC includes a read application, a descriptor application, and a reception application. The read application is configured such that the first RDMA NIC reads the WQEs from a first memory. The descriptor application is configured such that the first RDMA NIC: writes a portion of the WQEs directly from the first RDMA NIC to a second memory of the intermediary host device; and triggers a second RDMA NIC of the intermediary host device to process the portion of the WQEs stored in the second memory.
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