公开(公告)号：US12235707B2

公开(公告)日：2025-02-25

申请号：US17578273

申请日：2022-01-18

Applicant: Micron Technology, Inc.

Inventor： Jonathan S. Parry ,  Stephen L. Miller ,  Liang Yu

IPC: G06F1/3225 ,  G06F1/26 ,  G06F1/3212 ,  G06F1/3234 ,  G11C5/14 ,  G11C11/4074 ,  H01L23/00

Abstract: A technique to provide power management for multiple dice. The technique provides for determining for each respective die of the multiple dice, power consumption for operating each respective die; and generating a respective signal from each respective die that corresponds to the power consumption of each respective die. The technique further provides for converting each respective signal to a respective analog voltage to drive a common node; and utilizing a charge storage device coupled to the common node to accumulate the respective analog voltages from the dice, where the accumulated voltage indicates total power consumption of the dice.

公开(公告)号：US11935602B2

公开(公告)日：2024-03-19

申请号：US17738126

申请日：2022-05-06

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Liang Yu ,  Jeremy Binfet

IPC: G11C16/30 ,  G11C16/04 ,  G11C16/08 ,  H01L23/00 ,  H01L25/065

CPC classification number: G11C16/30 ,  G11C16/0483 ,  G11C16/08 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/48011 ,  H01L2224/48149 ,  H01L2224/48229 ,  H01L2224/4903 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/1438

Abstract: A memory device might include a controller configured to cause the memory device to generate a first sum of expected peak current magnitudes for a plurality of memory devices, and generate a second sum of expected peak current magnitudes for a subset of the plurality of memory devices, if the memory device were to initiate a next phase of an access operation in a selected operating mode; to compare the first sum to a first current demand budget for the plurality of the memory devices; to compare the second sum to a second current demand budget for the subset of memory devices; and to initiate the next phase of the access operation in the selected operating mode in response to the first sum being less than or equal to the first current demand budget and the second sum being less than or equal to the second current demand budget.

公开(公告)号：US20230195317A1

公开(公告)日：2023-06-22

申请号：US17988329

申请日：2022-11-16

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Liang Yu

IPC: G06F3/06

CPC classification number: G06F3/0613 ,  G06F3/0659 ,  G06F3/0679

Abstract: A memory device includes sets of memory dies. Each set of memory dies includes a memory dies associated with a respective channel of a plurality of channels, and each channel of the plurality of channels has a respective ready busy (RB) signal. The memory device further includes an input/output (I/O) expander to perform operations including receiving at least one command to perform clock synchronization associated with a clock signal with respect to the plurality of sets of memory dies, and in response to receiving the command, causing circuitry of the I/O expander to be configured to create an RB signal short with respect to a particular combination of channels. The clock synchronization is associated with peak power management (PPM) initialization.

公开(公告)号：US11670395B2

公开(公告)日：2023-06-06

申请号：US17249400

申请日：2021-03-01

Applicant: Micron Technology, Inc.

Inventor： Jeremy Binfet ,  Liang Yu

IPC: G11C29/00 ,  G11C29/50 ,  G06F1/3225

CPC classification number: G11C29/50 ,  G06F1/3225

Abstract: A memory device includes a first memory die of a plurality of memory dies, the first memory die comprising a first memory array and a first power management component, wherein the first power management component is configured to send a first test value to one or more other power management components on one or more other memory dies of the plurality of memory dies during a first power management cycle of a first power management token loop. The memory device further includes a second memory die of the plurality of memory dies, the second memory die comprising a second memory array and a second power management component, wherein the second power management component is configured to receive the first test value from the first power management component during the first power management cycle of the first power management token loop and send a second test value to the one or more other power management components on the one or more other memory dies of the plurality of memory dies during a second power management cycle of a second power management token loop. At least one of the first power management component or the second power management component is configured to compare the first test value and the second test value to a set of expected values to determine whether signal connections between the first power management component and the second power management component are functional.

公开(公告)号：US11532348B2

公开(公告)日：2022-12-20

申请号：US17110128

申请日：2020-12-02

Applicant: Micron Technology, Inc.

Inventor： Liang Yu ,  Jeremy Wayne Butterfield ,  Jeremy Binfet

IPC: G11C11/4074 ,  G11C11/4076 ,  G11C5/14 ,  G11C5/06 ,  G11C11/409

Abstract: A variety of applications can include multiple memory die packages configured to engage in peak power management (PPM) across the multiple packages of memory dies. A communication line coupled to each memory die in the multiple memory die packages can be used to facilitate the PPM. A global management die can start a communication sequence among the multiple memory die packages to share a current budget across the multiple memory die packages by driving a signal on the communication line. Local management dies can use the received signal having clock pulses driven by the global management die on the communication line to engage in the PPM. To engage in global PPM, each memory die can be structured, to be selected as the global management die or a local management die, with one or more controllers to interface with the multiple memory die packages and to handle current budget limits.

公开(公告)号：US20220276793A1

公开(公告)日：2022-09-01

申请号：US17745389

申请日：2022-05-16

Applicant: Micron Technology, Inc.

Inventor： Liang Yu ,  William C. Filipiak

IPC: G06F3/06 ,  G06K9/62

Abstract: A request is received from a host system to execute a portion of a memory management operation associated with a memory cell of a plurality of memory cells of one or more memory devices. A voltage parameter level associated with execution of the portion of the memory management operation is identified. A determination is made that a comparison of the voltage parameter level with a voltage parameter level threshold satisfies a condition. A power management action is performed in response to the condition being satisfied.

公开(公告)号：US20220137694A1

公开(公告)日：2022-05-05

申请号：US17578273

申请日：2022-01-18

Applicant: Micron Technology, Inc.

Inventor： Jonathan S. Parry ,  Stephen L. Miller ,  Liang Yu

IPC: G06F1/3225 ,  G06F1/3212 ,  G06F1/3234 ,  G11C5/14 ,  H01L23/00 ,  G11C11/4074 ,  G06F1/26

Abstract: A technique to provide power management for multiple dice. The technique provides for determining for each respective die of the multiple dice, power consumption for operating each respective die; and generating a respective signal from each respective die that corresponds to the power consumption of each respective die. The technique further provides for converting each respective signal to a respective analog voltage to drive a common node; and utilizing a charge storage device coupled to the common node to accumulate the respective analog voltages from the dice, where the accumulated voltage indicates total power consumption of the dice.

公开(公告)号：US20210294407A1

公开(公告)日：2021-09-23

申请号：US16821579

申请日：2020-03-17

Applicant: Micron Technology, Inc.

Inventor： Liang Yu ,  Jonathan Parry

IPC: G06F1/3234 ,  G06F1/3296 ,  G11C5/14

Abstract: A workload level in an incoming request queue is determined based on one or more operations requested by a host system for execution by a memory sub-system. Based on the workload level in the incoming request queue, a set of memory dies of the memory sub-system to be activated for execution of the one or more operations is identified. Based on a power budget level, a power mode configuration for a memory die of the set of memory dies is determined. One or more parameters of the memory die are configured to establish the power mode configuration.

公开(公告)号：US10884480B1

公开(公告)日：2021-01-05

申请号：US16548699

申请日：2019-08-22

Applicant: Micron Technology, Inc.

Inventor： Jonathan S. Parry ,  Stephen L. Miller ,  Liang Yu

IPC: G11C5/14 ,  G06F1/3234 ,  G06F1/3225

Abstract: A technique to provide power management for multiple dice. The technique provides for determining for each respective die of the multiple dice, power consumption for operating each respective die; and generating a respective analog current from each respective die that corresponds to the power consumption of each respective die. The technique further provides for driving each respective analog current onto a common node that results in a cumulative analog current; and utilizing the cumulative analog current at the common node to indicate total power consumption of the dice.

公开(公告)号：US20240290396A1

公开(公告)日：2024-08-29

申请号：US18444448

申请日：2024-02-16

Applicant: Micron Technology, Inc.

Inventor： Liang Yu ,  Jonathan S. Parry ,  Tal Sharifie

IPC: G11C16/30 ,  G06F12/02

CPC classification number: G11C16/30 ,  G06F12/0246

Abstract: Methods, systems, and devices for power management associated with memory and a controller are described. A memory system performs a power management operation that accounts for power usage by any combination of application specific integrated circuits (ASICs) and memory arrays. The power management operation includes multiple logical unit numbers (LUNs) assigned to a single ASIC, which increases a quantity of bits for communicating a power usage. An ASIC included in a memory system may utilize twice as many bits for communicating power usage information when compared to a NAND array. As part of the power management operation, an ASIC may transmit, to a controller, a first set of bits indicating a power usage of the ASIC, a first subset of the set of bits transmitted during a first instance of a token ring and a second subset of the set of bits transmitted during a second instance of the token ring.