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公开(公告)号：US20240154712A1
公开(公告)日：2024-05-09
申请号：US18415883
申请日：2024-01-18
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor： Bar Shapira , Ariel Almog , Dotan David Levi , Natan Manevich , Thomas Kernen , Liron Mula
IPC: H04J3/06
CPC classification number: H04J3/0638
Abstract: A system for maintaining a Precision Time Protocol (PTP) hardware clock, the system being operative in conjunction with a network device which is external to the system, the system comprising a controller to receive information characterizing a network peer oscillator frequency, wherein the information was extracted from an RX symbol rate, and to adjust the PTP Hardware Clock's frequency responsive to the information characterizing the network peer oscillator frequency.
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公开(公告)号：US20240089194A1
公开(公告)日：2024-03-14
申请号：US17990686
申请日：2022-11-20
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor： Ariel Almog , Eitan Zahavi , Idan Burstein , Zachy Haramaty , Aviv Barnea
IPC: H04L45/00 , H04L67/1097 , H04L69/22
CPC classification number: H04L45/22 , H04L45/66 , H04L67/1097 , H04L69/22
Abstract: A network adapter includes a port and one or more circuits. The port is to send packets to a network in accordance with a Remote Direct Memory Access over Converged Ethernet (RoCE) protocol. The one or more circuits are to decide whether a packet is permitted to undergo Adaptive Routing (AR) in being routed through the network, to mark the packet with an indication of whether the packet is permitted to undergo AR, and to send the marked packet to the network via the port.
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公开(公告)号：US11917045B2
公开(公告)日：2024-02-27
申请号：US17871937
申请日：2022-07-24
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor： Dotan David Levi , Arnon Sattinger , Natan Manevich , Wojciech Wasko , Ariel Almog , Bar Or Shapira
CPC classification number: H04L7/0012
Abstract: In one embodiment, a communication system includes network devices, each comprising a network interface to receive at least one data stream, a given network device being configured to recover a remote clock from the at least one data stream received by the given network device, a frequency synthesizer to generate a clock signal and output the clock signal to each of the network devices, wherein the given network device is configured to find a clock frequency differential between the clock signal and the recovered remote clock, and provide a control signal to the frequency synthesizer responsively to the clock frequency differential, the control signal causes the frequency synthesizer to adjust the clock signal so as to iteratively reduce an absolute value of the clock frequency differential between the clock signal and the recovered remote clock.
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公开(公告)号：US11876885B2
公开(公告)日：2024-01-16
申请号：US17335122
申请日：2021-06-01
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor： Dotan David Levi , Ariel Shahar , Shahaf Shuler , Ariel Almog , Eitan Hirshberg , Natan Manevich
IPC: H04L7/00
CPC classification number: H04L7/0091
Abstract: A timing system including timing circuitry which includes an arming queue, a clock work queue, and a clock completion queue. At least the clock work queue is to provide timing information, and the arming queue is to arm the clock work queue. Related apparatus and methods are also provided.
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公开(公告)号：US20230370305A1
公开(公告)日：2023-11-16
申请号：US17885604
申请日：2022-08-11
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor： Natan Manevich , Dotan David Levi , Wojciech Wasko , Ariel Almog , Bar Shapira
CPC classification number: H04L12/422 , G06F1/10 , H04J3/0667 , H04L12/43
Abstract: In one embodiment, a synchronized communication system includes a plurality of network devices, and clock connections to connect the network devices in a closed loop configuration, wherein the network devices are configured to distribute among the network devices a reference clock time from any selected one of the network devices.
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Patent Agency Ranking
公开(公告)号：US11706014B1
公开(公告)日：2023-07-18
申请号：US17579630
申请日：2022-01-20
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor： Natan Manevich , Dotan David Levi , Wojciech Wasko , Ariel Almog , Bar Shapira
IPC: H04L7/00
CPC classification number: H04L7/0012
Abstract: In one embodiment, a synchronized communication system includes a plurality of compute nodes, and clock connections to connect the compute nodes in a closed loop configuration, wherein the compute nodes are configured to distribute among the compute nodes a master clock frequency from any selected one of the compute nodes.
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公开(公告)号：US20220360423A1
公开(公告)日：2022-11-10
申请号：US17315396
申请日：2021-05-10
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor： Dotan David Levi , Wojciech Wasko , Natan Manevich , Teferet Geula , Amit Mandelbaum , Ariel Almog
Abstract: In one embodiment, a processing apparatus includes processing circuitry to process an event, a timestamping unit to generate a timestamp for the event, at least one register to store at least one parameter describing a hardware state of the processing circuitry, and timestamp correction processing circuitry to compute a time value as a correction to the generated timestamp responsively to the at least one parameter.
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公开(公告)号：US20220352998A1
公开(公告)日：2022-11-03
申请号：US17246730
申请日：2021-05-03
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor： Dotan David Levi , Wojciech Wasko , Natan Manevich , Roee Moyal , Eliel Peretz , Eran Ben Elisha , Ariel Almog , Teferet Geula , Amit Mandelbaum
Abstract: In one embodiment, an event processing system includes a clock configured to provide time values, and event processing circuitry, which is configured to generate a confidence level indicative of a degree of confidence of an accuracy of a timestamp, the timestamp being generated for an event responsively to a time value indicative of when an operation associated with the event occurred.
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公开(公告)号：US20140169170A1
公开(公告)日：2014-06-19
申请号：US13754912
申请日：2013-01-31
Applicant: MELLANOX TECHNOLOGIES LTD.
Inventor： Ariel Almog , Gil Bloch
IPC: H04L12/56
CPC classification number: H04L49/604 , H04L45/302 , H04L47/2441 , H04L47/32
Abstract: Network apparatus includes a plurality of interfaces, which are coupled to a network so as to receive and transmit data packets having respective link-layer headers and network-layer headers. Each link-layer header includes respective source and destination link-layer addresses and a link-layer priority value. Switching and routing logic is configured, responsively to the network-layer headers, to transfer each data packet from a respective ingress interface to a respective egress interface and to modify the source and destination link-layer addresses of the transferred data packet while copying the link-layer priority value from the ingress interface to the egress interface without modification.
Abstract translation: 网络装置包括多个接口，其耦合到网络，以便接收和发送具有相应链路层报头和网络层报头的数据分组。 每个链路层报头包括相应的源和目的链路层地址和链路层优先级值。 交换和路由逻辑被配置为响应于网络层报头，将每个数据分组从相应的入口接口传送到相应的出口接口，并且在复制链接的同时修改传送的数据分组的源和目的地链路层地址 从入口接口到出口接口的优先级值，无需修改。
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10.发明公开公开(公告)号：US20240231984A9
公开(公告)日：2024-07-11
申请号：US18074751
申请日：2022-12-05
Applicant: Mellanox Technologies, Ltd.
Inventor： Natan Manevich , Dotan David Levi , Shay Aisman , Ariel Almog , Ran Avraham Koren
IPC: G06F11/07
CPC classification number: G06F11/0757 , G06F11/0736
Abstract: A device includes a hardware block to perform a hardware process and internal logic coupled between a processing device, which executes instructions, and the hardware block. The internal logic can one of measure execution time or count clock cycles of at least a portion of the hardware process. The internal logic can further, in response to the measured execution time or the counted clock cycles satisfying a predetermined condition, provide data associated with the one of the execution time measurement or the clock cycles count to the processing device, the data being statistically indicative of a latency of data packets sent by the hardware process over a total time the hardware process executes.
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