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    Hybrid clock synchronization
    1.
    发明公开
    Hybrid clock synchronization 审中-公开

    公开(公告)号：US20240204897A1

    公开(公告)日：2024-06-20

    申请号：US18067767

    申请日：2022-12-19

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Natan Manevich ,  Dotan David Levi ,  Maciek Machnikowski ,  Wojciech Wasko ,  Bar Shapira ,  Jonathan Oliel ,  Ofir Sadeh

    IPC: H04J3/06

    CPC classification number: H04J3/0667

    Abstract: In one embodiment, a processing system includes an interface controller to receive a data signal from a remote link partner over a link, and recover a clock signal from the received data signal, frequency generation circuitry to receive the recovered clock signal, and output a local clock signal responsively to the received recovered clock signal, wherein the interface controller is configured to drive a transmit symbol rate responsively to the local clock signal, and a digital control loop including the interface controller and the frequency generation circuitry, wherein the interface controller is configured to identify a clock drift, generate a digital control signal responsively to the clock drift, and send the digital control signal to the frequency generation circuitry, which is configured to adjust a frequency of the local clock signal responsively to the digital control signal in order to reduce the clock drift.

    Software-controlled clock synchronization of network devices
    8.
    发明授权
    Software-controlled clock synchronization of network devices 有权

    公开(公告)号：US11606427B2

    公开(公告)日：2023-03-14

    申请号：US17120313

    申请日：2020-12-14

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Dotan David Levi ,  Avraham Ganor ,  Arnon Sattinger ,  Natan Manevich ,  Reuven Kogan ,  Artiom Tsur ,  Ariel Almog ,  Bar Shapira

    IPC: H04L67/1095 ,  G06F1/12 ,  G06F1/14

    Abstract: A synchronized communication system includes a plurality of network communication devices, one of which is designated as a root device and the others designated as slave devices. Each network communication device includes one or more ports and communications circuitry, which processes the communication signals received by the one or more ports so as to recover a respective remote clock from each of the signals. A synchronization circuit is integrated in the root device and provides a root clock signal, which is conveyed by clock links to the slave devices. A host processor selects one of the ports of one of the network communication devices to serve as a master port, finds a clock differential between the root clock signal and the respective remote clock recovered from the master port, and outputs, responsively to the clock differential, a control signal causing the synchronization circuit to adjust the root clock signal.

    PHYSICAL LAYER SYNCHRONIZATION
    9.
    发明申请
    PHYSICAL LAYER SYNCHRONIZATION 有权

    公开(公告)号：US20240373379A1

    公开(公告)日：2024-11-07

    申请号：US18225525

    申请日：2023-07-24

    Applicant: Mellanox Technologies, Ltd.

    Inventor： Natan Manevich ,  Dotan David Levi ,  Wojciech Wasko ,  Liron Mula ,  Ariel Almog ,  Bar Shapira ,  Guy Lederman

    IPC: H04W56/00

    Abstract: A system including an interconnect device coupled with one or more devices where the first device of the one or more devices is to transmit a control block for synchronization via a physical layer of a link coupled to the high-speed interconnect device, the control block comprising a header portion of bits corresponding to a header indicating the block is a control block and a data portion of bits indicating the control block is associated with time synchronization information. The interconnect device is to receive data, parse the data, determine the data is associated with the control block, determine a delay associated with the physical layer transmitting the control block and transmitting a signal responsive to receiving the control block and determining the delay.

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