公开(公告)号：US20240370322A1

公开(公告)日：2024-11-07

申请号：US18141595

申请日：2023-05-01

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Manjunath Gorentla Venkata ,  Vishwanath Venkatesan ,  Gil Bloch

IPC: G06F9/54 ,  H04L49/90

Abstract: Systems and methods herein are for message or data aggregation in computer networks in which at least one processor of a network module receives communication including messages having data, determines destination host machines for the messages, and aggregates a subset of the messages or the data to be transmitted to one of different destination host machines, where the aggregation is based at least in part on a bandwidth and a buffer availability associated with the one destination host machine, and where the buffer availability is determined from a status communication between the one destination host machine and the host machine.

公开(公告)号：US12137141B2

公开(公告)日：2024-11-05

申请号：US17858097

申请日：2022-07-06

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Daniel Marcovitch ,  Gil Bloch ,  Richard Graham ,  Yossef Itigin ,  Ortal Ben Moshe ,  Roman Nudelman

IPC: H04L12/70 ,  H04L41/0806 ,  H04L67/1097 ,  H04L67/12 ,  H04W48/08

Abstract: A network device includes a first interface, a second interface and circuitry. The first interface is configured to communicate at least with a first memory. The second interface is configured to communicate over a network with a peer network device coupled to a second memory. The circuitry is configured to (i) receive a request to transfer data over the network between the first memory and the second memory in accordance with a pattern of offsets to be accessed in the first memory or in the second memory, and (ii) transfer the data in accordance with the request.

公开(公告)号：US12135662B2

公开(公告)日：2024-11-05

申请号：US17858102

申请日：2022-07-06

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Daniel Marcovitch ,  Gil Bloch ,  Richard Graham ,  Yossef Itigin ,  Ortal Ben Moshe ,  Roman Nudelman

IPC: G06F13/28

Abstract: A Direct Memory Access (DMA) device includes an interface and a DMA engine. The interface is configured to communicate with a first memory and with a second memory. The DMA engine is configured to (i) receive a request to transfer data between the first memory and the second memory in accordance with a pattern of offsets to be accessed in the first memory or in the second memory, and (ii) transfer the data in accordance with the request.

公开(公告)号：US20240340242A1

公开(公告)日：2024-10-10

申请号：US18132519

申请日：2023-04-10

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Haggai Eran ,  Omer Shabtai ,  Gil Bloch ,  Michael Avimelech Gandelman Milgrom ,  Guy Rozenberg Kunievsky

IPC: H04L47/125

CPC classification number: H04L47/125

Abstract: A network device for load balancing in a multiplane network comprises a software stack that formats a data flow for transmission, and one or more circuits that identify the formatted data flow as a fixed data flow, and apply software-based load balancing to select a first plane, from among a plurality of planes of the multiplane network, for transmitting one or more data packets of the fixed data flow.

公开(公告)号：US20240297781A1

公开(公告)日：2024-09-05

申请号：US18176521

申请日：2023-03-01

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Manjunath Gorentla Venkata ,  Artem Yurievich Polyakov ,  Subhadeep Bhattacharya ,  Gil Bloch ,  William Ferrol Aderholdt

IPC: H04L9/08 ,  H04L9/14

CPC classification number: H04L9/0819 ,  H04L9/14 ,  H04L2209/125

Abstract: In one embodiment, a parallel computing system includes a key manager to assign symmetric memory keys to parallel computing jobs including a first symmetric memory key to a first parallel computing job, and a plurality of server nodes to execute parallel computing processes of the first parallel computing job, and cause registration of host memory regions of the server nodes with the assigned first symmetric memory key in corresponding network interface controllers of the server nodes so that different ones of the host memory regions are accessible with the first symmetric memory key by remote ones of the server nodes using remote direct memory access.

公开(公告)号：US20240015217A1

公开(公告)日：2024-01-11

申请号：US17858097

申请日：2022-07-06

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Daniel Marcovitch ,  Gil Bloch ,  Richard Graham ,  Yossef Itigin ,  Ortal Ben Moshe ,  Roman Nudelman

IPC: H04L67/1097

CPC classification number: H04L67/1097

Abstract: A network device includes a first interface, a second interface and circuitry. The first interface is configured to communicate at least with a first memory. The second interface is configured to communicate over a network with a peer network device coupled to a second memory. The circuitry is configured to (i) receive a request to transfer data over the network between the first memory and the second memory in accordance with a pattern of offsets to be accessed in the first memory or in the second memory, and (ii) transfer the data in accordance with the request.

公开(公告)号：US20230244629A1

公开(公告)日：2023-08-03

申请号：US17590339

申请日：2022-02-01

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Daniel Marcovitch ,  Dotan David Levi ,  Eyal Srebro ,  Eliel Peretz ,  Roee Moyal ,  Richard Graham ,  Gil Bloch ,  Sean Pieper

IPC: G06F13/42 ,  G06F7/76

CPC classification number: G06F13/42 ,  G06F7/76

Abstract: Devices, methods, and systems are provided. In one example, a device is described to include a device interface that receives data from at least one data source; a data shuffle unit that collects the data received from the at least one data source, receives a descriptor that describes a data shuffle operation to perform on the data received from the at least one data source, performs the data shuffle operation on the collected data to produce shuffled data, and provides the shuffled data to at least one data target.

公开(公告)号：US09634940B2

公开(公告)日：2017-04-25

申请号：US14662259

申请日：2015-03-19

Applicant: Mellanox Technologies Ltd.

Inventor： Zachy Haramaty ,  Eitan Zahavi ,  Freddy Gabbay ,  Diego Crupnicoff ,  Amiad Marelli ,  Gil Bloch

IPC: H04L12/803 ,  H04L12/703

CPC classification number: H04L47/122 ,  H04L45/28

Abstract: A method includes receiving in a network switch of a communication network communication traffic that originates from a source node and arrives over a route through the communication network traversing one or more preceding network switches, for forwarding to a destination node. In response to detecting in the network switch a compromised ability to forward the communication traffic to the destination node, a notification is sent to the preceding network switches. The notification is to be consumed by the preceding network switches and requests the preceding network switches to modify the route so as not to traverse the network switch.

公开(公告)号：US09197586B2

公开(公告)日：2015-11-24

申请号：US13754912

申请日：2013-01-31

Applicant: MELLANOX TECHNOLOGIES LTD.

Inventor： Ariel Almog ,  Gil Bloch

IPC: H04L12/851 ,  H04L12/931 ,  H04L12/823 ,  H04L12/725

CPC classification number: H04L49/604 ,  H04L45/302 ,  H04L47/2441 ,  H04L47/32

Abstract: Network apparatus includes a plurality of interfaces, which are coupled to a network so as to receive and transmit data packets having respective link-layer headers and network-layer headers. Each link-layer header includes respective source and destination link-layer addresses and a link-layer priority value. Switching and routing logic is configured, responsively to the network-layer headers, to transfer each data packet from a respective ingress interface to a respective egress interface and to modify the source and destination link-layer addresses of the transferred data packet while copying the link-layer priority value from the ingress interface to the egress interface without modification.

Abstract translation: 网络装置包括多个接口，其耦合到网络，以便接收和发送具有相应链路层报头和网络层报头的数据分组。 每个链路层报头包括相应的源和目的链路层地址和链路层优先级值。 交换和路由逻辑被配置为响应于网络层报头，将每个数据分组从相应的入口接口传送到相应的出口接口，并且在复制链接的同时修改传送的数据分组的源和目的地链路层地址 从入口接口到出口接口的优先级值，无需修改。

公开(公告)号：US20150263994A1

公开(公告)日：2015-09-17

申请号：US14207680

申请日：2014-03-13

Applicant: Mellanox Technologies Ltd.

Inventor： Zachy Haramaty ,  Noam Katz Abramovich ,  George Elias ,  Ido Bukspan ,  Benny Koren ,  Gil Bloch

IPC: H04L12/861 ,  H04L12/803 ,  H04L12/801

CPC classification number: H04L49/90 ,  H04L47/115 ,  H04L47/122 ,  H04L47/18 ,  H04L47/283 ,  H04L47/30 ,  H04L49/3036

Abstract: A switching apparatus includes multiple ports, each including a respective buffer, and a switch controller. The switch controller is configured to concatenate the buffers of at least an input port and an output port selected from among the multiple ports for buffering traffic of a long-haul link, which is connected to the input port and whose delay exceeds buffering capacity of the buffer of the input port alone, and to carry out end-to-end flow control for the long haul link between the output port and the input port.

Abstract translation: 开关装置包括多个端口，每个端口包括相应的缓冲器和开关控制器。 交换机控制器被配置为连接至少一个输入端口和从多个端口中选择的输出端口的缓冲器，用于缓冲连接到输入端口并且其延迟超过缓冲容量的长途链路的流量 单独输入端口的缓冲区，并为输出端口和输入端口之间的长途链路执行端到端流控制。