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    Process for producing gallium nitride crystal substrate, and gallium nitride crystal substrate
    1.
    发明授权
    Process for producing gallium nitride crystal substrate, and gallium nitride crystal substrate 有权
    制造氮化镓晶体基板的方法和氮化镓晶体基板

    公开(公告)号：US06824610B2

    公开(公告)日：2004-11-30

    申请号：US10106693

    申请日：2002-03-26

    Applicant: Masatomo Shibata ,  Naotaka Kuroda

    Inventor： Masatomo Shibata ,  Naotaka Kuroda

    IPC: C30B2504

    CPC classification number: H01L21/02491 ,  C30B25/02 ,  C30B25/18 ,  C30B29/40 ,  C30B29/406 ,  H01L21/02381 ,  H01L21/02389 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/02502 ,  H01L21/0254 ,  H01L21/02636 ,  Y10S117/915

    Abstract: A metal film is deposited on a starting substrate, which is any one of a single crystal sapphire substrate, a substrate comprising a single crystal gallium nitride film grown on a sapphire substrate, and a single crystal semiconductor substrate, and a gallium nitride film is deposited on the metal film to form a laminate substrate. By virtue of the above construction, after the growth of the gallium nitride film, the gallium nitride film can be easily separated from the starting substrate, and a gallium nitride crystal substrate, which has low defect density and has not been significantly contaminated with impurities, can be produced in a simple manner.

    Abstract translation: 金属膜沉积在起始衬底上，该起始衬底是单晶蓝宝石衬底，包括在蓝宝石衬底上生长的单晶氮化镓膜的衬底和单晶半导体衬底中的任何一个，并且沉积氮化镓膜 在金属膜上形成层叠基板。 通过上述结构，在氮化镓膜生长之后，氮化镓膜可以容易地与起始衬底分离，并且具有低缺陷密度且未被杂质显着污染的氮化镓晶体衬底， 可以简单地生产。

    Semiconductor Device
    6.
    发明申请
    Semiconductor Device 有权
    半导体器件

    公开(公告)号：US20080230807A1

    公开(公告)日：2008-09-25

    申请号：US11547402

    申请日：2005-03-30

    Applicant: Naotaka Kuroda ,  Masahiro Tanomura ,  Naoto Kurosawa

    Inventor： Naotaka Kuroda ,  Masahiro Tanomura ,  Naoto Kurosawa

    IPC: H01L29/73 ,  H01L23/34

    CPC classification number: H01L29/7371 ,  H01L23/367 ,  H01L27/0605 ,  H01L27/0664 ,  H01L29/66318 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor device having sufficiently high heat dissipation performance while inhibiting an increase in the area of a chip is provided. In semiconductor device 1, a plurality of HBTs 20 and a plurality of diodes 30 are one-dimensionally and alternately arranged on semiconductor substrate 10. Anode electrode 36 of diode 30 is connected to emitter electrode 27 of HBT 20 via common emitter wiring 42. Diode 30 works as heat dissipating elements dissipating to semiconductor substrate 10 the heat transmitted through common emitter wiring 42 from emitter electrode 27, and also works as a protection diode connected in parallel between an emitter and a collector of HBT 20.

    Abstract translation: 提供具有足够高的散热性能同时抑制芯片面积的增加的半导体器件。 在半导体器件1中，多个HBT 20和多个二极管30一维地交替地布置在半导体衬底10上。 二极管30的阳极电极36通过公共发射极配线42连接到HBT 20的发射极27。 二极管30作为散热元件散发到半导体衬底10上，从发射极27传播通过公共发射极配线42的热，并且还用作并联连接在HBT 20的发射极和集电极之间的保护二极管。

    FIELD EFFECT TRANSISTOR
    8.
    发明申请
    FIELD EFFECT TRANSISTOR 有权
    场效应晶体管

    公开(公告)号：US20100224910A1

    公开(公告)日：2010-09-09

    申请号：US12295004

    申请日：2007-03-29

    Applicant: Yuji Ando ,  Hironobu Miyamoto ,  Tatsuo Nakayama ,  Yasuhiro Okamoto ,  Takashi Inoue ,  Yasuhiro Murase ,  Kazuki Ota ,  Akio Wakejima ,  Naotaka Kuroda

    Inventor： Yuji Ando ,  Hironobu Miyamoto ,  Tatsuo Nakayama ,  Yasuhiro Okamoto ,  Takashi Inoue ,  Yasuhiro Murase ,  Kazuki Ota ,  Akio Wakejima ,  Naotaka Kuroda

    IPC: H01L29/80

    CPC classification number: H01L29/7787 ,  H01L29/2003

    Abstract: Disclosed is an HJFET 110 which comprises: a channel layer 12 composed of InyGa1-yN (0≦y≦1); a carrier supply layer 13 composed of AlxGa1-xN (0≦x≦1), the carrier supply layer 13 being provided over the channel layer 12 and including at least one p-type layer; and a source electrode 15S, a drain electrode 15D and a gate electrode 17 which are disposed facing the channel layer 12 through the p-type layer, and provided over the carrier supply layer 13. The following relational expression is satisfied: 5.6×1011x

    Abstract translation: 公开了一种HJFET 110，其包括：由In y Ga 1-y N（0＆lt; n 1; y＆n 1; 1）构成的沟道层12; 载体供给层13由Al x Ga 1-x N（0＆lt; n 1; x＆n 1; 1）组成，载流子供给层13设置在沟道层12上并且包括至少一个p型层; 以及源极电极15S，漏极电极15D和栅极电极17，其通过p型层面对沟道层12，并且设置在载流子供给层13上。满足以下关系式：5.6×10 11× NA×＆eegr×T [cm-2] <5.6×1013x，其中x表示载流子供应层的Al组成比，t表示p型层的厚度，NA表示杂质浓度，＆eegr; 表示活化比。

    FIELD EFFECT TRANSISTOR, AND MULTILAYERED EPITAXIAL FILM FOR USE IN PREPARATION OF FIELD EFFECT TRANSISTOR
    10.
    发明申请
    FIELD EFFECT TRANSISTOR, AND MULTILAYERED EPITAXIAL FILM FOR USE IN PREPARATION OF FIELD EFFECT TRANSISTOR 有权
    场效应晶体管和用于制备场效应晶体管的多层外延膜

    公开(公告)号：US20090045438A1

    公开(公告)日：2009-02-19

    申请号：US12159599

    申请日：2006-10-25

    Applicant: Takashi Inoue ,  Tatsuo Nakayama ,  Yuji Ando ,  Yasuhiro Murase ,  Kazuki Ota ,  Hironobu Miyamoto ,  Katsumi Yamanoguchi ,  Naotaka Kuroda ,  Akio Wakejima ,  Yasuhiro Okamoto

    Inventor： Takashi Inoue ,  Tatsuo Nakayama ,  Yuji Ando ,  Yasuhiro Murase ,  Kazuki Ota ,  Hironobu Miyamoto ,  Katsumi Yamanoguchi ,  Naotaka Kuroda ,  Akio Wakejima ,  Yasuhiro Okamoto

    IPC: H01L29/205 ,  H01L29/80

    CPC classification number: H01L29/7783 ,  H01L29/0607 ,  H01L29/155 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/42316 ,  H01L29/7787

    Abstract: In a group III nitride-type field effect transistor, the present invention reduces a leak current component by conduction of residual carriers in a buffer layer, and achieves improvement in a break-down voltage, and enhances a carrier confinement effect (carrier confinement) of a channel to improve pinch-off characteristics (to suppress a short channel effect). For example, when applying the present invention to a GaN-type field effect transistor, besides GaN of a channel layer, a composition-modulated (composition-gradient) AlGaN layer in which aluminum composition reduces toward a top gradually or stepwise is used as a buffer layer (hetero buffer). To gate length Lg of a FET to be prepared, a sum a of layer thicknesses of an electron supply layer and a channel layer is selected so as to fulfill Lg/a≧5, and in such a case, the layer thickness of the channel layer is selected in a range of not exceeding 5 times (about 500 Å) as long as a de Broglie wavelength of two-dimensional electron gas accumulated in the channel layer in room temperature.

    Abstract translation: 在III族氮化物型场效应晶体管中，本发明通过缓冲层中的残留载流子的传导来减少漏电流成分，并且可以实现击穿电压的提高，并提高载流子限制效应（载流子限制） 提高夹断特性的通道（抑制短路效应）。 例如，当将本发明应用于GaN型场效应晶体管时，除了沟道层的GaN之外，使用其中铝组成逐渐或逐步朝向顶部的组分调制（组成梯度）AlGaN层用作 缓冲层（杂质缓冲液）。 对于要制备的FET的栅极长度Lg，选择电子供给层和沟道层的层厚度的和a以满足Lg / a> = 5，并且在这种情况下， 在不超过5倍（约500）的范围内选择通道层，只要在室温下积聚在通道层中的二维电子气的德布罗意波长即可。

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