知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

22 records (took 0.015 seconds)

    Circuit simulator, circuit simulation method and program
    2.
    发明授权
    Circuit simulator, circuit simulation method and program 失效
    电路仿真器，电路仿真方法及程序

    公开(公告)号：US08332190B2

    公开(公告)日：2012-12-11

    申请号：US12517258

    申请日：2007-12-13

    Applicant: Masahiro Tanomura ,  Naotaka Kuroda ,  Masafumi Kawanaka

    Inventor： Masahiro Tanomura ,  Naotaka Kuroda ,  Masafumi Kawanaka

    IPC: G06F17/50 ,  H01L21/82

    CPC classification number: G06F17/5036

    Abstract: Characteristics of a circuit element are predicted accurately by taking account not only of the temperature variation due to self-heating of the element but also of temperature variation due to heat transmission from an adjoining heater element. With reference to an electric network supplied from an electric network input unit (2) and a heat network supplied from a heat network input unit (3), a simulation unit (4) determines a first heat generation temperature resulting from the amount of self-heat generation of that element and a second heat generating temperature resulting from the amount of heat flowing into that element from other elements, respectively, for a plurality of elements which make up a semiconductor integrated circuit, calculates the element temperature of that element based on the first and second heat generation temperatures, and then calculates the voltage value and the current value in the element at that element temperature based on previously provided data indicative of temperature dependency of that element.

    Abstract translation: 通过考虑由于元件的自加热引起的温度变化以及由于邻接的加热器元件的热传递引起的温度变化，可以精确地预测电路元件的特性。 参考从电网输入单元（2）提供的电网和从热网输入单元（3）提供的热网络，模拟单元（4）确定由自适应量产生的第一发热温度， 对于构成半导体集成电路的多个元件，该元件的发热和由分别从其它元件流入该元件的热量产生的第二发热温度基于该元件的温度来计算元件温度 第一和第二发热温度，然后基于先前提供的指示该元件的温度依赖性的数据计算该元件温度下的元件中的电压值和电流值。

    Transistor with heat dissipating means
    4.
    发明授权
    Transistor with heat dissipating means 有权
    具有散热装置的晶体管

    公开(公告)号：US07741700B2

    公开(公告)日：2010-06-22

    申请号：US11547402

    申请日：2005-03-30

    Applicant: Naotaka Kuroda ,  Masahiro Tanomura ,  Naoto Kurosawa

    Inventor： Naotaka Kuroda ,  Masahiro Tanomura ,  Naoto Kurosawa

    IPC: H01L27/082 ,  H01L27/102 ,  H01L29/70 ,  H01L31/11

    CPC classification number: H01L29/7371 ,  H01L23/367 ,  H01L27/0605 ,  H01L27/0664 ,  H01L29/66318 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor device having sufficiently high heat dissipation performance while inhibiting an increase in the area of a chip is provided. In semiconductor device 1, a plurality of HBTs 20 and a plurality of diodes 30 are one-dimensionally and alternately arranged on semiconductor substrate 10. Anode electrode 36 of diode 30 is connected to emitter electrode 27 of HBT 20 via common emitter wiring 42. Diode 30 works as heat dissipating elements dissipating to semiconductor substrate 10 the heat transmitted through common emitter wiring 42 from emitter electrode 27, and also works as a protection diode connected in parallel between an emitter and a collector of HBT 20.

    Abstract translation: 提供具有足够高的散热性能同时抑制芯片面积的增加的半导体器件。 在半导体器件1中，多个HBT 20和多个二极管30在半导体衬底10上一维地交替地布置。二极管30的阳极电极36通过公共发射极布线42连接到HBT 20的发射电极27.二极管 30作为散热元件散发到半导体衬底10上，从发射极27传播通过公共发射极配线42的热，并且还用作并联连接在HBT 20的发射极和集电极之间的保护二极管。

    Heterojunction bipolar transistor and method of producing the same
    8.
    发明授权
    Heterojunction bipolar transistor and method of producing the same 有权
    异质结双极晶体管及其制造方法

    公开(公告)号：US06924201B2

    公开(公告)日：2005-08-02

    申请号：US10447934

    申请日：2003-05-29

    Applicant: Masahiro Tanomura ,  Hidenori Shimawaki ,  Yosuke Miyoshi ,  Fumio Harima

    Inventor： Masahiro Tanomura ,  Hidenori Shimawaki ,  Yosuke Miyoshi ,  Fumio Harima

    IPC: H01L29/73 ,  H01L21/308 ,  H01L21/331 ,  H01L29/205 ,  H01L29/737

    CPC classification number: H01L29/66318 ,  H01L29/7371

    Abstract: A heterojunction bipolar transistor of the present invention is produced from a wafer including a substrate and a collector layer of a first conductivity type, a base layer of a second conductivity type and an emitter layer of the first conductivity type sequentially laminated on the substrate in this order. First, the wafer is etched up to a preselected depth of the collector layer via a first photoresist, which is formed at a preselected position on the emitter layer, serving as a mask. Subsequently, the collector layer etched with at least the sidewalls of the base layer and collector layer, which are exposed by the first etching step, and a second photoresist covering part of the surface of the collector layer contiguous with the sidewalls serving as a mask.

    Abstract translation: 本发明的异质结双极晶体管由包括第一导电类型的基板和集电极层，第二导电类型的基极层和第一导电类型的发射极层的晶片制成，该晶体管在该基板上顺序层叠在基板上 订购。 首先，将晶片经由形成在发射极层上的预选位置上的第一光致抗蚀剂蚀刻到集电极层的预选深度，作为掩模。 随后，用至少通过第一蚀刻步骤曝光的基底层和集电体层的侧壁蚀刻的集电极层和覆盖与用作掩模的侧壁相邻的集电极层的表面的一部分的第二光致抗蚀剂。

    Balun circuit and integrated circuit device
    10.
    发明授权
    Balun circuit and integrated circuit device 有权
    平衡电路和集成电路器件

    公开(公告)号：US08076993B2

    公开(公告)日：2011-12-13

    申请号：US12529891

    申请日：2008-03-11

    Applicant: Yasuhiro Hamada ,  Shuya Kishimoto ,  Kenichi Maruhashi ,  Masaharu Ito ,  Masahiro Tanomura ,  Naoyuki Orihashi

    Inventor： Yasuhiro Hamada ,  Shuya Kishimoto ,  Kenichi Maruhashi ,  Masaharu Ito ,  Masahiro Tanomura ,  Naoyuki Orihashi

    IPC: H03H7/42 ,  H01P3/08

    CPC classification number: H01P5/10

    Abstract: A balun circuit comprising first through third CPW lines becoming signal I/O ports, a first differential transmission line for linking the central conductor of the second CPW line and the ground conductor of the first CPW line and for linking the ground conductor of the second CPW line and the central conductor of the first CPW line, a second differential transmission line for linking the central conductors of the first and third CPW lines and for linking the ground conductors of the first and third CPW lines, and a joint for connecting at least two ground conductors of the first through third CPW lines. The differential transmission line has a first line formed in a dielectric layer on a substrate, a second line arranged in the underlying layer, and an underlying line at a fixed potential arranged between the substrate and the second line.

    Abstract translation: 包括第一至第三CPW线变为信号I / O端口的平衡 - 不平衡转换电路，用于将第二CPW线的中心导体和第一CPW线的接地导体连接并用于连接第二CPW的接地导体的第一差分传输线 线和第一CPW线的中心导体，用于连接第一和第三CPW线的中心导体并用于连接第一和第三CPW线的接地导体的第二差分传输线，以及用于连接至少两个 第一至第三CPW线的接地导体。 差分传输线具有形成在基板上的电介质层中的第一线，布置在下层中的第二线，以及布置在基板和第二线之间的固定电位的底线。

Patent Agency Ranking