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    DYNAMIC MEMORY ALLOCATION USING A SHARED FREE LIST
    1.
    发明申请
    DYNAMIC MEMORY ALLOCATION USING A SHARED FREE LIST 有权

    公开(公告)号：US20240411680A1

    公开(公告)日：2024-12-12

    申请号：US18330007

    申请日：2023-06-06

    Applicant: Mellanox Technologies, Ltd.

    Inventor： Gil Kremer ,  Roee Moyal ,  Igor Voks ,  Liel Peled ,  Eliel Peretz ,  Ariel Shahar

    IPC: G06F12/02

    Abstract: Apparatuses, systems, and techniques for dynamic memory allocation using a shared free list. A user tag is received, and a hashed user tag is generated. A first reference to an entry in a second data structure is identified in a first data structure using the hashed user tag. The entry includes multiple user tags. Responsive to determining that the multiple user tags do not include the user tag, a memory address is identified in a third data structure. The memory address is removed from the third data structure. Memory is allocated for a user context associated with the user tag at the memory address. The user tag is added to the second data structure.

    Efficient packet reordering using hints
    2.
    发明授权
    Efficient packet reordering using hints 有权

    公开(公告)号：US11792139B2

    公开(公告)日：2023-10-17

    申请号：US17582047

    申请日：2022-01-24

    Applicant: Mellanox Technologies, Ltd.

    Inventor： Boris Pismenny ,  Ben Ben Ishay ,  Gal Yefet ,  Gil Kremer ,  Avi Urman ,  Yorai Itzhak Zack ,  Khalid Manaa ,  Liran Liss

    IPC: H04L69/22 ,  H04L49/90 ,  H04L49/9057

    CPC classification number: H04L49/9057 ,  H04L49/9042 ,  H04L69/22

    Abstract: A peripheral device coupled to a host includes a network interface, a packet processor, and a Data Processing Unit (DPU). The packet processor receives from a communication network, via the network interface, packets that originated from a source in an original order and received at the peripheral device in as order different from the original order. The packet processor splits the received packets into headers and payloads, sends the payloads for storage in a host memory and sends the headers without the payloads for storage in a DPU memory, and based on the headers produces a hint indicative of processing to be applied to the headers, by the DPU, for identifying the original order. Based on the hint, the DPU identifies the original order of the packets by applying the processing indicated by the hint to respective headers in the DPU memory, and notifies the host of the original order.

    SYSTEM AND METHOD FOR LOW LATENCY PACKET PROCESSING
    3.
    发明申请
    SYSTEM AND METHOD FOR LOW LATENCY PACKET PROCESSING 有权

    公开(公告)号：US20250028658A1

    公开(公告)日：2025-01-23

    申请号：US18224262

    申请日：2023-07-20

    Applicant: Mellanox Technologies, Ltd.

    Inventor： Ortal Ben Moshe ,  Roee Moyal ,  Shay Aisman ,  Gil Bloch ,  Ariel Shahar ,  Roman Nudelman ,  Gil Kremer ,  Yossef Itigin ,  Lior Narkis

    IPC: G06F13/16 ,  G06F9/54

    Abstract: Systems and methods are described herein for processing data packets. An example network adapter may include a network interface operatively coupled to a communication network and a packet processing circuitry operatively coupled to the network interface. The packet processing circuitry may receive, via the network interface, a message; retrieve, via a packet processing circuitry, a work queue element (WQE) index identifying a position of a WQE in a receive queue; determine that the message is associated with a small payload; process the message without consuming the WQE; receive, via the network interface, a subsequent message; and process the subsequent message using the WQE. In this way, the systems and methods describe herein reduce the latency in processing of the data packets.

    Efficient end-to-end credit requestor-responder system
    4.
    发明申请
    Efficient end-to-end credit requestor-responder system 有权

    公开(公告)号：US20250023668A1

    公开(公告)日：2025-01-16

    申请号：US18351544

    申请日：2023-07-13

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Roee Moyal ,  Gil Kremer ,  Ortal Ben Moshe ,  Ariel Shahar

    IPC: H04L1/1607 ,  H04L1/08 ,  H04L47/34

    Abstract: In one embodiment, a first network device includes a host interface to receive messages from a host device, packet processing circuitry to send a batch of the messages to a second network device without waiting for an acknowledgement receipt from the second network device after sending each message, one message in the batch having a maximum message sequence number (MSN), receive a given acknowledgement receipt from the second network device indicating that all the messages in the batch have been received and including credit data indicating that there is no space in a receive work queue of the second network device for receiving an additional message, and send the additional message having an MSN greater than the maximum MSN to the second network device responsively to receiving the given acknowledgement receipt and based on the credit data indicating that there is no space in the receive work queue.

    Coalescing packets based on hints generated by network adapter
    5.
    发明授权
    Coalescing packets based on hints generated by network adapter 有权

    公开(公告)号：US12218860B2

    公开(公告)日：2025-02-04

    申请号：US16932765

    申请日：2020-07-19

    Applicant: Mellanox Technologies, Ltd.

    Inventor： Gal Yefet ,  Avi Urman ,  Gil Kremer ,  Lior Narkis ,  Boris Pismenny

    IPC: H04L49/90 ,  G06F9/54 ,  H04L47/2441 ,  H04L69/22

    Abstract: A network node includes a network adapter and a host. The network adapter is coupled to a communication network. The host includes a processor running a client process and a communication stack, and is configured to receive packets from the communication network, and classify the received packets into respective flows that are associated with respective chunks in a receive buffer, to distribute payloads of the received packets among the chunks so that payloads of packets classified to a given flow are stored in a given chunk assigned to the given flow, and to notify the communication stack of the payloads in the given chunk, for transferring the payloads in the given chunk to the client process.

    STRIDED MESSAGE BASED RECEIVE BUFFER
    7.
    发明申请
    STRIDED MESSAGE BASED RECEIVE BUFFER 有权

    公开(公告)号：US20250030649A1

    公开(公告)日：2025-01-23

    申请号：US18224258

    申请日：2023-07-20

    Applicant: Mellanox Technologies, Ltd.

    Inventor： Ortal Ben Moshe ,  Roee Moyal ,  Shay Aisman ,  Gil Bloch ,  Ariel Shahar ,  Roman Nudelman ,  Gil Kremer ,  Yossef Itigin ,  Lior Narkis

    IPC: H04L49/9057

    Abstract: Systems and methods are described herein for processing data packets. An example network adapter may include a network interface operatively coupled to a communication network and packet processing circuitry operatively coupled to the network interface. The packet processing circuitry is configured to receive, via the network interface, a plurality of data packets associated with a message; determine, for each data packet, at least one corresponding reserved stride in a strided buffer; store each data packet in the at least one corresponding reserved stride; process the strided buffer upon storing the plurality of data packets in a corresponding plurality of reserved strides; and generate a completion notification indicating that the plurality of data packets in the strided buffer has been processed.

    Efficient packet reordering using hints
    9.
    发明公开
    Efficient packet reordering using hints 审中-公开

    公开(公告)号：US20230239257A1

    公开(公告)日：2023-07-27

    申请号：US17582047

    申请日：2022-01-24

    Applicant: Mellanox Technologies, Ltd.

    Inventor： Boris Pismenny ,  Ben Ben Ishay ,  Gal Yefet ,  Gil Kremer ,  Avi Urman ,  Yorai Itzhak Zack ,  Khalid Manaa ,  Liran Liss

    IPC: H04L49/9057 ,  H04L69/22 ,  H04L49/90

    CPC classification number: H04L49/9057 ,  H04L69/22 ,  H04L49/9042

    Abstract: A peripheral device coupled to a host includes a network interface, a packet processor, and a Data Processing Unit (DPU). The packet processor receives from a communication network, via the network interface, packets that originated from a source in an original order and received at the peripheral device in as order different from the original order. The packet processor splits the received packets into headers and payloads, sends the payloads for storage in a host memory and sends the headers without the payloads for storage in a DPU memory, and based on the headers produces a hint indicative of processing to be applied to the headers, by the DPU, for identifying the original order. Based on the hint, the DPU identifies the original order of the packets by applying the processing indicated by the hint to respective headers in the DPU memory, and notifies the host of the original order.

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