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公开(公告)号:US12218860B2
公开(公告)日:2025-02-04
申请号:US16932765
申请日:2020-07-19
Applicant: Mellanox Technologies, Ltd.
Inventor: Gal Yefet , Avi Urman , Gil Kremer , Lior Narkis , Boris Pismenny
IPC: H04L49/90 , G06F9/54 , H04L47/2441 , H04L69/22
Abstract: A network node includes a network adapter and a host. The network adapter is coupled to a communication network. The host includes a processor running a client process and a communication stack, and is configured to receive packets from the communication network, and classify the received packets into respective flows that are associated with respective chunks in a receive buffer, to distribute payloads of the received packets among the chunks so that payloads of packets classified to a given flow are stored in a given chunk assigned to the given flow, and to notify the communication stack of the payloads in the given chunk, for transferring the payloads in the given chunk to the client process.
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公开(公告)号:US11438266B2
公开(公告)日:2022-09-06
申请号:US16780940
申请日:2020-02-04
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor: Avi Urman , Lior Narkis , Noam Bloch
Abstract: A communication apparatus includes a host interface, connected to a peripheral component bus so as to communicate with a CPU and a memory of a host computer. A network interface is connected to a network. Packet processing circuitry is configured to receive from a first interface a data packet including a set of one or more headers that include header fields having respective values, to identify, responsively to at least one of the header fields, a corresponding entry in a header modification table that specifies a header modification operation, to modify the set of headers in accordance with the header modification operation, to check whether the entry specifies an additional header modification operation, to output the modified set of headers if the entry does not specify an additional header modification operation, and, if the entry specifies an additional header modification operation, to feed-back the modified set of headers.
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公开(公告)号:US11258885B2
公开(公告)日:2022-02-22
申请号:US16708470
申请日:2019-12-10
Applicant: Mellanox Technologies, Ltd.
Inventor: Avi Urman , Lior Narkis , Noam Bloch
Abstract: One embodiment includes a network device, including hardware parsers to receive data of a header section of a packet, the header section including respective headers, parser configuration registers to store a default parsing configuration data set, wherein at least one of the hardware parsers is configured to parse at least one of the headers responsively to the default parsing configuration data set, yielding first parsed data, a packet processing engine to select a selected parsing configuration data set from a selection of parsing configuration data sets responsively to the first parsed data, cause loading of the selected parsing configuration data set into the parser configuration registers, and wherein ones of the hardware parsers are configured to parse respective ones of the headers responsively to the selected parsing configuration data set, yielding second parsed data, and process the packet responsively to the second parsed data.
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公开(公告)号:US20210385169A1
公开(公告)日:2021-12-09
申请号:US17409625
申请日:2021-08-23
Applicant: Mellanox Technologies Ltd.
Inventor: Avi Urman , Lior Narkis , Gil Kremer , Saar Tarnopolsky , Dotan David Levi
IPC: H04L12/823 , H04L29/06 , H04L12/707 , H04L12/815
Abstract: Apparatuses, systems, and techniques to eliminate redundant data packets. In at least one embodiment, a communication apparatus generates redundant data packets, and sends them in multiple packet streams. In at least one embodiment, a communication apparatus eliminates redundant data packets from received packet streams.
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公开(公告)号:US20240364633A1
公开(公告)日:2024-10-31
申请号:US18307830
申请日:2023-04-27
Applicant: Mellanox Technologies, Ltd.
Inventor: Michael Weiner , Amit Hermony , Avi Urman , Idan Burstein , Yuval Shpigelman
IPC: H04L47/122 , H04L43/0852 , H04L47/11
CPC classification number: H04L47/122 , H04L43/0852 , H04L47/11
Abstract: A network device includes one or more ports, processing circuitry, and a memory-network congestion controller. The one or more ports are to connect to a network. The processing circuitry is to run a plurality of processing tasks that access a shared memory, one or more of the processing tasks including communicating one or more packet flows over the network. The memory-network congestion controller is to identify a memory-access congestion, which occurs in accessing the shared memory by one or more of the processing tasks, and to alleviate the memory-access congestion by causing a reduction in a communication rate of at least one of the packet flows.
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公开(公告)号:US12068968B2
公开(公告)日:2024-08-20
申请号:US17588295
申请日:2022-01-30
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor: Gal Yefet , Saar Tarnopolsky , Avi Urman , Dotan David Levi , Elena Agostini
IPC: H04L47/2441 , H04L47/6295 , H04L69/22
CPC classification number: H04L47/2441 , H04L69/22
Abstract: In one embodiments, data communication system include a communication apparatus, which is configured to receive data from different user equipment devices a schedule of time periods, and packetize the data from respective ones of the user equipment devices for respective ones of the time periods into packets, a memory including a plurality of buffers, and a network interface controller configured to receive the packets from the communication apparatus, and scatter respective portions of the data belonging to respective groups of successive ones of the time periods to the buffers, responsively to a static set of steering rules, and timing information of respective ones of the packets, and wherein each respective portion of the data is scattered to the buffers a same scatter pattern.
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公开(公告)号:US11792139B2
公开(公告)日:2023-10-17
申请号:US17582047
申请日:2022-01-24
Applicant: Mellanox Technologies, Ltd.
Inventor: Boris Pismenny , Ben Ben Ishay , Gal Yefet , Gil Kremer , Avi Urman , Yorai Itzhak Zack , Khalid Manaa , Liran Liss
IPC: H04L69/22 , H04L49/90 , H04L49/9057
CPC classification number: H04L49/9057 , H04L49/9042 , H04L69/22
Abstract: A peripheral device coupled to a host includes a network interface, a packet processor, and a Data Processing Unit (DPU). The packet processor receives from a communication network, via the network interface, packets that originated from a source in an original order and received at the peripheral device in as order different from the original order. The packet processor splits the received packets into headers and payloads, sends the payloads for storage in a host memory and sends the headers without the payloads for storage in a DPU memory, and based on the headers produces a hint indicative of processing to be applied to the headers, by the DPU, for identifying the original order. Based on the hint, the DPU identifies the original order of the packets by applying the processing indicated by the hint to respective headers in the DPU memory, and notifies the host of the original order.
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公开(公告)号:US11621920B2
公开(公告)日:2023-04-04
申请号:US17902834
申请日:2022-09-04
Applicant: Mellanox Technologies, Ltd.
Inventor: Avi Urman , Lior Narkis , Omri Kahalon
IPC: H04L47/20 , H04L47/2466 , H04L47/2475 , G06F9/455 , H04L47/783 , H04L47/12
Abstract: A network adapter includes a network interface, a host interface and processing circuitry. The network interface is configured to connect to a communication network. The host interface is configured to communicate with a host processor running multiple application programs. The processing circuitry includes one or more bandwidth-control policers, and is configured to receive from the communication network a packet destined to a given application program among the application programs running on the host processor, to associate a bandwidth-control policer with the packet, selected from among the bandwidth-control policers, and to apply the selected bandwidth-control policer to the packet to produce a policer result.
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公开(公告)号:US11190462B2
公开(公告)日:2021-11-30
申请号:US16693302
申请日:2019-11-24
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor: Dotan David Levi , Avi Urman , Lior Narkis
IPC: G06F15/16 , H04L12/939 , H04L12/861 , H04W28/04 , H04L29/06 , H04L12/879
Abstract: Communication apparatus includes a host interface and a network interface, which receives from a packet communication network at least one packet stream including a sequence of data packets, which include headers containing respective sequence numbers and data payloads containing slices of the data segment having a predefined, fixed size per slice. Packet processing circuitry is configured to receive the data packets from the network interface, and to map the data payloads of the data packets in the at least one packet stream, using a linear mapping of the sequence numbers, to respective addresses in the buffer.
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公开(公告)号:US20210344600A1
公开(公告)日:2021-11-04
申请号:US16865567
申请日:2020-05-04
Applicant: Mellanox Technologies, Ltd.
Inventor: Avi Urman , Lior Narkis , Noam Bloch , Eyal Srebro , Shay Aisman
IPC: H04L12/801 , H04L12/835 , H04L12/823
Abstract: A network adapter includes a host interface, a network interface, a memory and packet processing circuitry. The memory holds a shared buffer and multiple queues allocated to the multiple host processors. The packet processing circuitry is configured to receive from the network interface data packets destined to the host processors, to store payloads of at least some of the data packets in the shared buffer, to distribute headers of at least some of the data packets to the queues, to serve the data packets to the host processors by applying scheduling among the queues, to detect congestion in the data packets destined to a given host processor among the host processors, and, in response to the detected congestion, to mitigate the congestion in the data packets destined to the given host processor, while retaining uninterrupted processing of the data packets destined to the other host processors.
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