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公开(公告)号：US20160156364A1
公开(公告)日：2016-06-02
申请号：US14922203
申请日：2015-10-26
Applicant: Mediatek Inc.
Inventor： Pang-Ning Chen , Yu-Li Hsueh , Jian-Yu Ding
CPC classification number: H03L7/1976 , H03K21/023 , H03K23/42 , H03L7/081 , H03L7/1974
Abstract: A fractional dividing module includes an output clock generating circuit, for receiving an input clock signal and generating an output clock signal according to a first control signal, comprising a first delay unit, for delaying the input clock signal to generate a delayed input clock signal; and a selecting unit, for selecting one of the input clock signal and the delayed input clock signal to generate the output clock signal according to the first control signal; and a control circuit, for dividing the output clock signal to generate the first control signal according to a dividing control signal, wherein the dividing control is adjusted to control a frequency ratio between the output clock signal and the input clock signal.
Abstract translation: 分数分割模块包括输出时钟产生电路，用于接收输入时钟信号并根据第一控制信号产生输出时钟信号，包括第一延迟单元，用于延迟输入时钟信号以产生延迟的输入时钟信号; 以及选择单元，用于选择所述输入时钟信号和所述延迟的输入时钟信号之一，以根据所述第一控制信号产生所述输出时钟信号; 以及控制电路，用于根据划分控制信号对输出时钟信号进行分频以产生第一控制信号，其中调整分频控制以控制输出时钟信号和输入时钟信号之间的频率比。
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2.发明授权公开(公告)号：US10141921B2
公开(公告)日：2018-11-27
申请号：US15378056
申请日：2016-12-14
Applicant: MEDIATEK INC.
Inventor： Pang-Ning Chen , Yu-Li Hsueh
IPC: H03L7/06 , H03K5/145 , H03B5/32 , H03K5/19 , H03K19/21 , H03L7/089 , H03L7/099 , G06F1/02 , G06F1/08
Abstract: A signal generator generates an output signal according to an oscillating signal. The signal generator has a plurality of edge sampling circuits and an edge combining circuit. Each of the edge sampling circuits receives the oscillating signal, samples the oscillating signal to obtain at least one of a rising edge and a falling edge in one cycle of the oscillating signal, and outputs a sampled signal using the at least one of the rising edge and the falling edge. The edge combining circuit combines a plurality of sampled signals generated by the edge sampling circuits, respectively, to generate the output signal.
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公开(公告)号：US09755653B2
公开(公告)日：2017-09-05
申请号：US14737603
申请日：2015-06-12
Applicant: MEDIATEK Inc.
Inventor： Pang-Ning Chen , Yu-Li Hsueh , Pi-An Wu
CPC classification number: H03L7/089 , H03K3/356043 , H03K5/1565 , H03L7/085
Abstract: A phase detector including a first latch and a control circuit is provided. The first latch generates a first output signal and a second output signal in response to a phase difference between a first input signal and a second input signal. Each of the first and second output signals includes first phase information and second phase information of the phase difference. The control circuit generates a phase indicating signal in response to the first phase information of the phase difference. The phase indicating signal indicates a relative position between the first input signal and the second input signal.
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Patent Agency Ranking
公开(公告)号：US20180123575A1
公开(公告)日：2018-05-03
申请号：US15717919
申请日：2017-09-27
Applicant: MEDIATEK INC.
Inventor： Po-Chun Huang , Chao-Ching Hung , Yu-Li Hsueh , Pang-Ning Chen
CPC classification number: H03K5/15046 , H03K21/026 , H04B1/04
Abstract: A quadrature clock generating apparatus connected to a local oscillator generating an input clock signal and an inverted input clock signal includes a fractional dividing circuit and a quadrature signal generating circuit. The fractional dividing circuit is configured for receiving the input clock signal and the inverted input clock signal, and for performing frequency-division upon the input clock signal and the inverted input clock signal to generate a frequency-divided clock signal according to a fractional dividing parameter. The quadrature signal generating circuit is configured for receiving the input clock signal, the inverted input clock signal, and the frequency-divided clock signal to generate a plurality of quadrature clock signals.
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公开(公告)号：US09685966B2
公开(公告)日：2017-06-20
申请号：US14922203
申请日：2015-10-26
Applicant: MEDIATEK INC.
Inventor： Pang-Ning Chen , Yu-Li Hsueh , Jian-Yu Ding
CPC classification number: H03L7/1976 , H03K21/023 , H03K23/42 , H03L7/081 , H03L7/1974
Abstract: A fractional dividing module includes an output clock generating circuit, for receiving an input clock signal and generating an output clock signal according to a first control signal, comprising a first delay unit, for delaying the input clock signal to generate a delayed input clock signal; and a selecting unit, for selecting one of the input clock signal and the delayed input clock signal to generate the output clock signal according to the first control signal; and a control circuit, for dividing the output clock signal to generate the first control signal according to a dividing control signal, wherein the dividing control is adjusted to control a frequency ratio between the output clock signal and the input clock signal.
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公开(公告)号：US20160126961A1
公开(公告)日：2016-05-05
申请号：US14737603
申请日：2015-06-12
Applicant: MEDIATEK Inc.
Inventor： Pang-Ning Chen , Yu-Li Hsueh , Pi-An Wu
CPC classification number: H03L7/089 , H03K3/356043 , H03K5/1565 , H03L7/085
Abstract: A phase detector including a first latch and a control logic is provided. The first latch generates a first output signal and a second output signal in response to a phase difference between a first input signal and a second input signal. Each of the first and second output signals includes first phase information and second phase information of the phase difference. The control circuit generates a phase indicating signal in response to the first phase information of the phase difference. The phase indicating signal indicates a relative position between the first input signal and the second input signal.
Abstract translation: 提供了包括第一锁存器和控制逻辑器件的相位检测器。 第一锁存器响应于第一输入信号和第二输入信号之间的相位差产生第一输出信号和第二输出信号。 第一和第二输出信号中的每一个包括相位差的第一相位信息和第二相位信息。 控制电路根据相位差的第一相位信息产生相位指示信号。 相位指示信号表示第一输入信号和第二输入信号之间的相对位置。
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公开(公告)号：US10374588B2
公开(公告)日：2019-08-06
申请号：US15717919
申请日：2017-09-27
Applicant: MEDIATEK INC.
Inventor： Po-Chun Huang , Chao-Ching Hung , Yu-Li Hsueh , Pang-Ning Chen
Abstract: A quadrature clock generating apparatus connected to a local oscillator generating an input clock signal and an inverted input clock signal includes a fractional dividing circuit and a quadrature signal generating circuit. The fractional dividing circuit is configured for receiving the input clock signal and the inverted input clock signal, and for performing frequency-division upon the input clock signal and the inverted input clock signal to generate a frequency-divided clock signal according to a fractional dividing parameter. The quadrature signal generating circuit is configured for receiving the input clock signal, the inverted input clock signal, and the frequency-divided clock signal to generate a plurality of quadrature clock signals.
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8.发明申请公开(公告)号：US20170207779A1
公开(公告)日：2017-07-20
申请号：US15378056
申请日：2016-12-14
Applicant: MEDIATEK INC.
Inventor： Pang-Ning Chen , Yu-Li Hsueh
CPC classification number: H03K5/145 , G06F1/022 , G06F1/08 , H03B5/32 , H03K5/19 , H03K19/21 , H03L7/0891 , H03L7/099
Abstract: A signal generator generates an output signal according to an oscillating signal. The signal generator has a plurality of edge sampling circuits and an edge combining circuit. Each of the edge sampling circuits receives the oscillating signal, samples the oscillating signal to obtain at least one of a rising edge and a falling edge in one cycle of the oscillating signal, and outputs a sampled signal using the at least one of the rising edge and the falling edge. The edge combining circuit combines a plurality of sampled signals generated by the edge sampling circuits, respectively, to generate the output signal.
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