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公开(公告)号：US20160156364A1
公开(公告)日：2016-06-02
申请号：US14922203
申请日：2015-10-26
Applicant: Mediatek Inc.
Inventor： Pang-Ning Chen , Yu-Li Hsueh , Jian-Yu Ding
CPC classification number: H03L7/1976 , H03K21/023 , H03K23/42 , H03L7/081 , H03L7/1974
Abstract: A fractional dividing module includes an output clock generating circuit, for receiving an input clock signal and generating an output clock signal according to a first control signal, comprising a first delay unit, for delaying the input clock signal to generate a delayed input clock signal; and a selecting unit, for selecting one of the input clock signal and the delayed input clock signal to generate the output clock signal according to the first control signal; and a control circuit, for dividing the output clock signal to generate the first control signal according to a dividing control signal, wherein the dividing control is adjusted to control a frequency ratio between the output clock signal and the input clock signal.
Abstract translation: 分数分割模块包括输出时钟产生电路，用于接收输入时钟信号并根据第一控制信号产生输出时钟信号，包括第一延迟单元，用于延迟输入时钟信号以产生延迟的输入时钟信号; 以及选择单元，用于选择所述输入时钟信号和所述延迟的输入时钟信号之一，以根据所述第一控制信号产生所述输出时钟信号; 以及控制电路，用于根据划分控制信号对输出时钟信号进行分频以产生第一控制信号，其中调整分频控制以控制输出时钟信号和输入时钟信号之间的频率比。
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公开(公告)号：US09685966B2
公开(公告)日：2017-06-20
申请号：US14922203
申请日：2015-10-26
Applicant: MEDIATEK INC.
Inventor： Pang-Ning Chen , Yu-Li Hsueh , Jian-Yu Ding
CPC classification number: H03L7/1976 , H03K21/023 , H03K23/42 , H03L7/081 , H03L7/1974
Abstract: A fractional dividing module includes an output clock generating circuit, for receiving an input clock signal and generating an output clock signal according to a first control signal, comprising a first delay unit, for delaying the input clock signal to generate a delayed input clock signal; and a selecting unit, for selecting one of the input clock signal and the delayed input clock signal to generate the output clock signal according to the first control signal; and a control circuit, for dividing the output clock signal to generate the first control signal according to a dividing control signal, wherein the dividing control is adjusted to control a frequency ratio between the output clock signal and the input clock signal.
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